izmit escort escort ankara adana escort

 FAQ •  Search •  Register •  Login 

All times are UTC + 1 hour [ DST ]




Post new topic Reply to topic  [ 6 posts ] 
Author Message
 Post subject: A Problem about uCOS III on SAMA5D2-Xplained board
PostPosted: Thu Apr 27, 2017 3:25 am 
Offline

Joined: Thu Mar 16, 2017 12:30 pm
Posts: 23
Hi,
I download the demo of Micrium_SAMA5D2-XULT_OS3. After compiled on EWARM platform to generate OS3.bin code. It can run well on my SAMA5D2-Xplained board. It just run in internal ram.Now i want to link the bin code to run in external ram(DDR). I edit the SRAM.icf file, but the bin code cannot run after recompiled. I do not know why? here is my ddram.icf file.
Code:
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x0;
define symbol __ICFEDIT_region_IROM1_end__   = 0x0;
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x200000;
define symbol __ICFEDIT_region_IRAM1_end__   = 0x21FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_ERAM1_end__   = 0x23FFFFFF;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x24000000;
define symbol __ICFEDIT_region_ERAM2_end__   = 0x24FFFFFF;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_intvec__   = 0x100;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_fiqstack__ = 0x60;
define symbol __ICFEDIT_size_abtstack__ = 0x40;
define symbol __ICFEDIT_size_undstack__ = 0x40;
define symbol __ICFEDIT_size_sysstack__ = 0x40;
define symbol __ICFEDIT_size_cstack__   = 0x3000;
define symbol __ICFEDIT_size_heap__     = 0x200;
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
define region VEC_region = mem:[from __ICFEDIT_region_IRAM1_start__ size __ICFEDIT_size_intvec__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__+__ICFEDIT_size_intvec__ to __ICFEDIT_region_IRAM1_end__];
define region DDRAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__];
define region DDRAM_NOCACHE_region = mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__];

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
define block HEAP      with alignment = 4, size = __ICFEDIT_size_heap__     { };

initialize by copy with packing=none { readwrite };
do not initialize  { readonly section .noinit };
/* Warning: ICC still considers the sections below as zero-initialized, by default. */
do not initialize  { section .region_sram };
do not initialize  { section .region_ddr };
do not initialize  { section .region_ddr_nocache };

place in VEC_region { section .vectors };
place in RAM_region { section .region_sram };
place in DDRAM_region { readonly };
place in DDRAM_region { section .cstartup };
place in DDRAM_region { readwrite, block IRQ_STACK, block HEAP, block FIQ_STACK, block ABT_STACK, block UND_STACK, block SYS_STACK, block CSTACK };
place in DDRAM_region { section .region_ddr };
place in DDRAM_NOCACHE_region { section .region_ddr_nocache };

I use this icf file to compile the project to generate a bin file OS3_ddram.bin. When i flash to QSPI flash and boot by bootstrap . It just print as blow.
Code:
####################
RomBOOT
-- Kaitong Bootloader V1.0 --
Softpack v2.3
Built for sama5d2-xult
Processor: SAMA5D27-CU
Processor clock: 396 MHz
Master clock: 132 MHz
MMU is enabled
I-Cache is enabled
D-Cache is enabled

QSPI: Load image from qspi flash to ddram.
QSPI: Copy from 0xA0000 to 0x2000000...
#########################################################################################################
QSPI: Done to load image.
QSPI: Run to 0x2000000.

#####################
Undefined Instruction
#####################

####################
Prefetch Fault reason is: debug event
prefetch Fault occured at address: 0xd0007744

Prefetch Fault status register value: 0x2
####################

####################
Prefetch Fault reason is: debug event
prefetch Fault occured at address: 0xd0007878

Prefetch Fault status register value: 0x2
####################

How does this happen? Can you please point the problem. Thank you!

HW: SAMA5D2-Xplained


Top
 Profile  
Reply with quote  
 Post subject: Re: A Problem about uCOS III on SAMA5D2-Xplained board
PostPosted: Thu Apr 27, 2017 12:22 pm 
Offline

Joined: Thu Mar 16, 2017 12:30 pm
Posts: 23
I know, it is the problem about the region of VEC_region!
Thanks!


Top
 Profile  
Reply with quote  
 Post subject: Re: A Problem about uCOS III on SAMA5D2-Xplained board
PostPosted: Fri Apr 28, 2017 1:24 am 
Offline

Joined: Thu Apr 19, 2007 10:15 pm
Posts: 1432
Location: USA
Maybe there is an issue "about the region of VEC_region", but the bootloader seems to be using bogus addresses.
xzp114 wrote:
Code:
QSPI: Load image from qspi flash to ddram.
QSPI: Copy from 0xA0000 to 0x2000000... 
   ... 
QSPI: Run to 0x2000000.
0x000A0000 is not the address for "qspi flash", but rather the middle of ECC ROM (0x00040000- 0x000FFFFF).
0x02000000 is not the start of DRAM, but is undefined memory space (0x00C00000-0x0FFFFFFF).

Then jumping into the undefined memory will produce unpredicatble results such as "Undefined Instruction".

Regards


Top
 Profile  
Reply with quote  
 Post subject: Re: A Problem about uCOS III on SAMA5D2-Xplained board
PostPosted: Fri Apr 28, 2017 3:30 am 
Offline

Joined: Thu Mar 16, 2017 12:30 pm
Posts: 23
blue_z wrote:
0x000A0000 is not the address for "qspi flash", but rather the middle of ECC ROM (0x00040000- 0x000FFFFF).
0x02000000 is not the start of DRAM, but is undefined memory space (0x00C00000-0x0FFFFFFF).

Then jumping into the undefined memory will produce unpredicatble results such as "Undefined Instruction".

Thanks for your reply!
The 0xA0000 is just the offset of QSPI0 address(0xD0000000);
The 0x2000000 is just a clerical mistake, is 0x20000000.
The problem is the region of VEC_region , it should be in the start of ddr address, and my APP can boot by my bootstrapper.


Top
 Profile  
Reply with quote  
 Post subject: Re: A Problem about uCOS III on SAMA5D2-Xplained board
PostPosted: Thu May 11, 2017 10:17 am 
Offline

Joined: Wed Jul 22, 2015 2:47 am
Posts: 2
xzp114 wrote:
blue_z wrote:
0x000A0000 is not the address for "qspi flash", but rather the middle of ECC ROM (0x00040000- 0x000FFFFF).
0x02000000 is not the start of DRAM, but is undefined memory space (0x00C00000-0x0FFFFFFF).

Then jumping into the undefined memory will produce unpredicatble results such as "Undefined Instruction".

Thanks for your reply!
The 0xA0000 is just the offset of QSPI0 address(0xD0000000);
The 0x2000000 is just a clerical mistake, is 0x20000000.
The problem is the region of VEC_region , it should be in the start of ddr address, and my APP can boot by my bootstrapper.


@xzp114,You solve this problems?How to solve,thanks


Top
 Profile  
Reply with quote  
 Post subject: Re: A Problem about uCOS III on SAMA5D2-Xplained board
PostPosted: Mon May 22, 2017 9:03 am 
Offline

Joined: Thu Mar 16, 2017 12:30 pm
Posts: 23
Quote:
You solve this problems?How to solve,thanks

The VEC_region should be in the start of ddr address!


Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 6 posts ] 

All times are UTC + 1 hour [ DST ]


Who is online

Users browsing this forum: No registered users and 1 guest


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to: