Does anyone have examples of the hw reset and watchdog code required to fix this problem?

Thanks

Does this help?:

This function is referred to in my previous post in this thread.

#include <linux/linkage.h>
#include <asm/assembler.h>
.balign 64
ENTRY(power_down_reset)
powerdownnow:
mrs r0, cpsr
orr r0, r0, #0x80 //128 Disable interrupts
msr cpsr_c, r0

ldr r0, =0xFEFFEA10
ldr r1, =1 //SDRAM controller self refresh
str r1, [r0]

ldr r0, =0xFEFFFC14 //PMC Periph clock disable reg
ldr r1, =0x7FFFFFFC // disable all but AIC and SYSC
str r1, [r0]

b firstpoint

secondpoint:
ldr r2, =0xFEFFFD00
ldr r3, =0xA5000005 //system reset

nop
nop
nop
nop
nop
nop
nop
nop

str r3, [r2]
nop
mov pc, lr // should never get here

firstpoint:
nop


b secondpoint

Hi,

Has anybody implemented the interrupt Trap the for Hardware reset and wdt reset?

Lucas.

IMHO, A cleaner solution would be to run from SRAM.
For a Non-OS-based application I placed the C function that performs the reset in the SRAM by using the "ramfunc" attribute. Otherwise I'm running my application from SDRAM. This way, I don't need to go into assembly.

Nothing against assembly programming but I think keeping these things in C helps makes it more flexible, readable and better integrated.

I don't know how this can be done for Linux but it should be possible.

Hi,

all worked fine for me aith Kernel 2.6.30.5.
Now I switched to Kernel 3.0.0.
I use the sam code in both kernels for reset, but unfortunately with the new kernel the system hangs at reset:

Last line on the console: "Rstarting system"
It seems to be strange, because no RomBOOT Message appears...?
It seems that the Reset isn´t executed by the AT91SAM9G20 !

If I insert 2 printk´s before I execute the Assembler Code the system reset works ???
I try to exchange the printk with a mdelay, but this doesn´t fix the problem....

Please have a look at my code:

Regards
Manuel

Is there anybody who could help me ?

[code]
#define CP15_CR_I (1 << 12)

#define SYS_VIRT_OFS (-0x01000000)
#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
#define SDRAMC_TR 0x0004
#define SDRAMC_LPR 0x0010
#define SDRAMC_LPCB_POWER_DOWN 2

#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
#define RSTC_CR 0x0000
#define RSTC_PROCRST (1 << 0)
#define RSTC_PERRST (1 << 2)
#define RSTC_KEY (0xa5 << 24)

void soft_user_reset (void)
{
// ATTENTION: Without the following 2 printk´s - the reset sometimes won´t work ????
//printk("SDRAMC_BASE = %04X\n", SDRAMC_BASE);
//printk("RSTC_BASE = %04X\n", RSTC_BASE);

//soft_user_reset
//;disable IRQs
asm("MRS r0, CPSR");
asm("ORR r0, r0, #0x80");
asm("MSR CPSR_c, r0");

asm("mov r0, #0");
asm("mcr p15, 0, r0, c7, c5, 0"); //@ flush I-cache

asm("mrc p15, 0, r0, c1, c0, 0");
asm("orr r0, r0, #(1 << 12)"); //asm("orr r0, r0, #CP15_CR_I");
asm("mcr p15, 0, r0, c1, c0, 0"); //@ enable I-cache

// @ preload constants
asm("ldr r0, =0xFEFFEA00"); //SDRAMC_BASE
asm("ldr r1, =0xFEFFFD00"); //RSTC_BASE

asm("mov r2, #1"); //;change refresh rate to block all data accesses
asm("mov r3, #2"); //;prepare power down command
asm("ldr r4, =0xA5000005"); //;prepare proc_reset and periph_reset


asm(".balign 32"); //@ align to cache line
//;change refresh rate to block all data accesses (in the ARM pipeline)
asm("str r2, [r0, #0x0004]"); //@ disable SDRAM access
//;perform power down command (in the ARM pipeline)
asm("str r3, [r0, #0x0010]"); //@ power down SDRAM
//;perform proc_reset and periph_reset (in the ARM pipeline)
asm("str r4, [r1, #0x0000]"); //@ reset processor

//Endless lopp
asm("b .");
}
[/code]

Don't poke 0x2 into 0xFFFFEA10, this places the SDRAM into very low power mode, from which it seems to get stuck during reset. Why not just disable the LPM altogether to assure a clean reset?

- asm("mov r3, #2"); //;prepare power down command
+ asm("mov r3, #0"); //;disable low power function

In linux, you can patch the reset routine with this:

===
--- at91sam9_alt_reset.S (revision 10727)
+++ at91sam9_alt_reset.S (working copy)
@@ -31,7 +31,7 @@
ldr r1, .at91_va_base_rstc_cr

mov r2, #1
- mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
+ mov r3, #AT91_SDRAMC_LPCB_DISABLE
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST

.balign 32 @ align to cache line

===

Let me know how this works for you. It works for me on an AT91SAM9G20 running Linux kernel 3.0.

Take care,
-Chris

Looking at the kernel source provided for my project, it seems that the code provided by colonel-panic is provided. (At the moment I'm not sure where my source tree came from, I inherited this project)

That being said, the solution only covers when a system reboot occurs. I am still seeing issues when hitting the external reset line and from the 9G20 documentation it looks like you can catch the rstc_irq and hopefully perform this same action. The problem I'm running into is figuring out how to register the interrupt. I'm wanting to add the register to at91sam9260.c in at91sam9260_initialize but since its a System Peripheral I'm not quite sure how to go about that.

Are all system peripherals masked together and then you need to resolve which was triggered? I don't see in the mach-at91 directory any situations where any of the other system peripherals using interrupt service routines. Any ideas?

Edit:
I also am assuming that since the Watchdog timer triggers the Reset Controller, figuring out my previous issue would move me closer to resolving the Errata in the situation where the Watchdog causes the reset.