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 Post subject: Need help with PWM on Atmel9G45
PostPosted: Wed Jul 20, 2011 6:57 am 
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Joined: Thu Dec 30, 2010 6:49 pm
Posts: 38
Hi,

I am using dev Kit based on atmel9g45 board and have written a pwm application to generated 22KHz PWM with varying duty cycle. This was working fine and now all of a sudden it has stopped working... i am flashing the same code on different boads but they don't seem to work. Below is lower level driver calls

static int pwm_int(void)
{
int major;
printk("<1> \n Loading PWM module ...");
major = register_chrdev(MY_MAJOR,"dbgpwm",&pwm_fops);
if (major < 0)
{
printk(KERN_ALERT "\n Registering PWM char device failed with %d\n", MY_MAJOR);
unregister_chrdev(MY_MAJOR,"dbgpwm");
return major;
}

printk(KERN_INFO "\n PWM device installed, with major number %d\n",
MY_MAJOR);
printk(KERN_INFO
"\n Create device node using 'mknod /dev/dbgpwm c %d 0'\n",MY_MAJOR);

//system('mknod /dev/dbgpwm c 240 0');
printk(KERN_INFO "\n Memory allocation ");
baseptr = ioremap(AT91SAM9G45_BASE_PWMC, 1024);
printk(KERN_INFO "\n pwm_ioctl called");
at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */

// PWM Channel enable - Eanble all channels
writeb(0x0F, baseptr+0x04);
return 0;

}
int pwm_ioctl(struct inode *inode,
struct file *file,
unsigned int ioctl_num, /* number and param for ioctl */
unsigned long ioctl_param)

{


//Setting PWM_MR - Mode register value
switch(ioctl_num)
{
case PWM_ON:
memset(&pwmst, 0, sizeof(PWM_CONF));
if(copy_from_user(&pwmst, (void __user *)ioctl_param, sizeof(PWM_CONF)))
return -EFAULT;

printk(KERN_INFO "\n PWM_ON cmd called");
printk("<1> \n PWM = %d ch= %d", pwmst.pwmval, pwmst.pwmch);


switch(pwmst.pwmch)
{

case 0:
printk(KERN_INFO "\n Channel 1 ");
// Enabling CPOL in PWM_CMR at offset 0xFFFB8200
writeb(0x02, baseptr+0x201);

//Enabling duty cycle - PWM_CDTY ; Take care of "Endianess"
writew((0x0010* pwmst.pwmval), baseptr+0x204);

// PWM_CPRD - Channel period - Take care of "Endianess"
writew(0x061F, baseptr+0x208);
break;


....

}

Above code snippet shows register configuration for channel 0. I have the same code repeated for different channels. Can anyone please let me know is something is wrong ? Do i need to change something in kernel?

Thanks
Prashanth


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