I'm trying to configure the Atmel driver for the LG LB070WV6 LCD display. I was hoping that someone has done this before and can give me values that work. I also have a question about what needs to be modified.

I changed the section in at91sam9263_devices.c as follows:

#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
static u64 lcdc_dmamask = DMA_BIT_MASK(32);
static struct atmel_lcdfb_info lcdc_data;

static struct resource lcdc_resources[] = {
[0] = {
.start = AT91SAM9263_LCDC_BASE,
.end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = AT91SAM9263_ID_LCDC,
.end = AT91SAM9263_ID_LCDC,
.flags = IORESOURCE_IRQ,
},
};

static struct platform_device at91_lcdc_device = {
.name = "atmel_lcdfb",
.id = 0,
.dev = {
.dma_mask = &lcdc_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &lcdc_data,
},
.resource = lcdc_resources,
.num_resources = ARRAY_SIZE(lcdc_resources),
};

void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
{
if (!data)
return;

at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC28, 0); /* LCDD23 */

lcdc_data = *data;
platform_device_register(&at91_lcdc_device);
}
------
I also changed the LCD Controller section in board-sam9263ek.c as follows:
/*
* LCD Controller
*/
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "LB070WV6 @ 60",
.refresh = 60,
.xres = 800, .yres = 480,
.pixclock = KHZ2PICOS(36000),

.left_margin = 1, .right_margin = 33,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,

.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
};

static struct fb_monspecs at91fb_default_monspecs = {
.manufacturer = "LG",
.monitor = "LB070WV6",

.modedb = at91_tft_vga_modes,
.modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
.hfmin = 15000,
.hfmax = 64000,
.vfmin = 50,
.vfmax = 150,
};

#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)

static void at91_lcdc_power_control(int on)
{
//at91_set_gpio_value(AT91_PIN_PA30, on);
at91_set_gpio_value(AT91_PIN_PD11, on);
at91_set_gpio_value(AT91_PIN_PD10, on);
}

/* Driver datas */
static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2,
.default_monspecs = &at91fb_default_monspecs,
.atmel_lcdfb_power_control = at91_lcdc_power_control,
.guard_time = 1,
};

----
I think that I am missing something as the configuration of the pins in at91sam9263_devices.c states the functions in comments and I haven't found code that would tell the driver which one is vertical sync?

>>I think that I am missing something as the configuration of the pins in at91sam9263_devices.c states the functions in comments and I haven't found code that would tell the driver which one is vertical sync?

You'll find that PC0 is defined as LCDVSYNC by the 9263 peripheral muxing hardware, it's the "Peripheral A" column of "PIO Controller C", per the manual. You have very little control over this pin assignment, so you need to wire it appropriately to the panel.

You'd have to configure the LCD controller to generate the appropriate signal on that pin. For instance the width, and front/back porch settings.

If you have a 16-bit display, you might want to take a serious look at what you're doing with PC4..PC19, if you need to get LCDD0..LCDD15 to the panel.

Thank you. I now understand the peripheral muxing hardware. I've been trying to set the LCDDOTCK, but as I change the value of ".pixclock = KHZ2PICOS(33000)" found in board-sam9263-ek.c the pixel clock changes from 20nSec to 40nSec with no steps in between. For my LCD the range needs to be between 28.49 and 36.90 nSec. The manual makes mention of this being related to the "LCDC Core clock" but I don't know how to adjust it's frequency.

Well that means you might have to play musical chairs with the PLLA/PLLB settings, and the PCK and MCK for the CPU and Memory/Peripherals.

I'd guess from the numbers you're probably using a 100 MHz MCK, giving you a 20 ns granularity. With 133 MHz, that would be around 15 ns, so 30 ns would be attainable.

What kind of SDRAM are you using?

Most of the EK dev boards use the -75 PC133 CAS3 versions.

MT48LC16M16A2
http://download.micron.com/pdf/datashee ... MSDRAM.pdf

We are using the MT48LC16M16A2. We have kept most of the components of the AT91SAM9263-ek except for the screen. What do I need to do to change the PLLA? Will it change timing for other peripherals?

What is your crystal speed? 18.432 MHz or 16.36766 MHz

Are you using USB? Requires PLLB generate a multiple of 48 MHz (*1,2,4)

What speed is your CPU running, can run? 200, 240 MHz?

Can you provide the PLLA, PLLB, MCKR you are currently using?

Other than USB, most of the other peripherals can generate their own clocks (USART, SPI, I2C) from whatever the system is using.

For instance a PCK of 240 MHz, MCK of 120 MHz, from PLLA, would get you a LCD setting of 33.33 ns. You could stick PLLB at ~96 MHz for USB.

Like I said, you'll need to play musical chairs with the settings until they meet all your criterion, I don't currently have enough information about the settings/limitations in your system to provide some specific register settings.

EDIT : Digging in the manual the max rate for the SDRAM appears to be 100 MHz, dropping the rate to hit your ~30ns goal for the LCD might not be desirable. You might want to talk to an ATMEL rep about what the real max frequency is for the CPU and SDRAM. Some places they suggest the CPU runs at up to 240 MHz.

AT91 LCD App Note
http://atmel.com/dyn/resources/prod_doc ... oc6300.pdf

AT91 PLL Tool
http://www.atmel.com/dyn/resources/prod ... AM_pll.htm

I just wanted to say thanks for the help and post a follow up.

For the LCD driver in the AT91SAM9263 it can handle dot clock frequencies of 50mhz, 25mhz and on down. Basically this means a minimum period of 20ns and multiples of that, i.e. 40ns, 60ns. Most seven inch 800X600 and 800X480 displays run close to 33mhz and can NOT be supported by the AT91SAM9263. There are a few odd displays that claim to support a wider range and we are requesting samples of these displays. The little display that ships with the EK needs a dot clock of 180ns which is an even multiple of 20ns so it works.

Last follow up. It turns out that the information above is incorrect. The LB070WV6 does work with a wider range of frequencies. First how did I figure this out?

First step, recompile the Angstrom x11-gpe-image with the program fbset.
---
IMAGE_INSTALL = "\
${XSERVER} \
task-base-extended \
angstrom-x11-base-depends \
angstrom-gpe-task-base \
angstrom-gpe-task-settings \
kernel-modules \
hal \
fbset \
angstrom-gpe-task-pim \
${ANGSTROM_EXTRA_INSTALL}"
--
Next change the board-sam9263ek.c file to have the correct resolution and as good of numbers as you can guess. I know there is a way to calculate these numbers, but I didn't figure out the formula. Then boot up the board with a serial console cable and login on the command line. Now try some fbset values:

fbset -t 25000 120 120 10 10 1 1

It is doesn't work try different values. When you find values that work plug them into the struct fb_videomode in the file board-sam9263ek.c.

Following are the values that worked for the LB070WV6.

/*
* LCD Controller
*/
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "LB070WV6 @ 60",
.refresh = 60,
.xres = 840, .yres = 480,
.pixclock = KHZ2PICOS(25000),

.left_margin = 120, .right_margin = 120,
.upper_margin = 10, .lower_margin = 10,
.hsync_len = 1, .vsync_len = 1,

.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
};

static struct fb_monspecs at91fb_default_monspecs = {
.manufacturer = "LG",
.monitor = "LB070WV6",

.modedb = at91_tft_vga_modes,
.modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
.hfmin = 5000,
.hfmax = 85000,
.vfmin = 5,
.vfmax = 150,
};

#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)

static void at91_lcdc_power_control(int on)
{
//at91_set_gpio_value(AT91_PIN_PA30, on);
at91_set_gpio_value(AT91_PIN_PD11, on);
mdelay(50);
at91_set_gpio_value(AT91_PIN_PD10, on);
}

/* Driver datas */
static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2,
.default_monspecs = &at91fb_default_monspecs,
.atmel_lcdfb_power_control = at91_lcdc_power_control,
.guard_time = 2,
};