Hi,
I'm trying to get the USART working in sync mode at 6Mb/s. It appeared, that to achieve that I have to move the RX buffer to the internal SRAM.
I allocate the buffer with request_mem_region and map it with ioremap to obtain the virtual address for kernel.
However, after that, the dma_sync_single_for_cpu called from atmel_rx_from_dma causes the kernel panic.
So my question is:
1. Is it necessary to synchronize the DMA buffers located in the internal SRAM?
2. If yes, what are the proper functions to perform this synchronization?
EDIT:
I've checked the system diagram (Fig. 2-1 in the doc6221 - http://www.atmel.com/dyn/resources/prod ... oc6221.pdf ) and I can see, that the SRAM is accessible via the switch matrix, and therefore via the cache system, so synchronization is probably necessary...
EDIT2:
I have analyzed how the dma_sync_single_for_cpu works and it seems, that I can call directly:
__dma_single_cpu_to_dev
Unfortunately it appears, that the above function does not accept neither ioremapped virtual address of the buffer nor the virtual address obtained via __phys_to_virt from the physical address of the buffer.
Use of both triggers the bug at: http://lxr.linux.no/linux+v3.0.4/arch/a ... ing.c#L451
EDIT3:
I have found, that that my buffer
is allocated at 0x200000 (SRAM0) and ioremapped to 0xc4890000, while
high_memory is at 0xc4000000. Therefore my buffer address fails the
test of address validity at http://lxr.linux.no/linux+v3.0.4/arch/a ... ory.h#L292 .

It could suggest that accesses to my buffer bypass the cache (as it is above high_memory location), but when I simply skip the synchronization routines, I still get corrupted data.
On comp.arch.embedded I received a suggestion that the problem may be associated with handling of accesses by a Bus Matrix...
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TIA & Regards,
Wojtek