I dont have an answer, but I am very interested. There is a patch from David Brownell that I havent tried and there is a patch I got from TimeSys which I did. Its for 2.6.22 kernels. It fails for interval < 1 ms though (at CONFIG_HZ 250, so its doing something...)
Here is a pasting of my conversation with DB:
>
> I will make this as brief as I can. We are developing a product based on the
> at91sam9260 process. We would like to use POSIX timers with better than the
> 10 or 4 ms intervals you can get if the high res timers arent available. I
> looked around hard and the only reference I can find to someone having
> implemented the necessary code is a patch you submitted,
>
>
http://www.spinics.net/lists/arm-kernel/msg42268.html
Note that you'll also need a PIT clockevent conversion patch, like
the one I appended to this message, on sam9 chips.
> I can't even work out what kernel version it is patched against. Can you
> tell me
>
> - if this patch has migrated up-stream any where ?
No, and in that form it won't.
> - what versions of the kernel it is patched against ?
I don't recall. Try it and see if it applies against your
version. I suspect either 2.6.23 or 2.6.24 should work;
current GIT has some issues since the platform devices file
has changed.
> I not an expert on kernels or low level hardware - if there is any other
> info you can give me on trying to make this work for my board, it would be
> appreciated. I am happy to run test etc.
>
> Cheers and thanks
>
> Gertjan
>
========== CUT HERE
Update at91sam926x PIT to use generic time and clockevent infrastructure:
- Clocksource gives sub-microsecond timestamp precision, assuming
memory is clocked at over 16 MHz. It's less than a 32 bit counter,
unless it's is also generating IRQs.
- Clockevent device works supports periodic mode only; no oneshot
support from this hardware. No IRQs generated unless it's the
active clocksource.
Later, another timer (probably from a TC module) can provide a oneshot
clockevent device to get NO_HZ and High-Res-Timer behaior.
This also updates the timekeeping to use the actual master clock rate
on the system, instead of compile-time <asm/arch/timex.h> constants
matching what Atmel's EK boards use. (Product boards may well differ!)
Plus cleanup: rename "*_timer*" symbols to "*_pit*" (there are other
timers, but only one PIT); shorter lines; remove needless CPP stuff;
make several symbols static; etc.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
arch/arm/mach-at91/Kconfig | 8 +
arch/arm/mach-at91/at91sam926x_time.c | 169 ++++++++++++++++++++++++----------
2 files changed, 128 insertions(+), 49 deletions(-)
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,15 +12,23 @@ config ARCH_AT91RM9200
config ARCH_AT91SAM9260
bool "AT91SAM9260 or AT91SAM9XE"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9261
bool "AT91SAM9261"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9263
bool "AT91SAM9263"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
config ARCH_AT91X40
bool "AT91x40"
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-at91/at91sam926x_time.c
+ * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
*
* Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
* Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
@@ -8,16 +8,12 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-
-#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
#include <asm/mach/time.h>
#include <asm/arch/at91_pit.h>
@@ -26,88 +22,163 @@
#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
+static u32 pit_cycle; /* write-once */
+static u32 pit_cnt; /* access only w/system irq blocked */
+
+
/*
- * Returns number of microseconds since last timer interrupt. Note that interrupts
- * will have been disabled by do_gettimeofday()
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * Clocksource: just a monotonic counter of mck/16 cycles.
+ * We don't care whether or not PIT irqs are enabled.
*/
-static unsigned long at91sam926x_gettimeoffset(void)
+static cycle_t read_pit_clk(void)
{
- unsigned long elapsed;
- unsigned long t = at91_sys_read(AT91_PIT_PIIR);
+ unsigned long flags;
+ u32 elapsed;
+ u32 t;
- elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t); /* hardware clock cycles */
+ raw_local_irq_save(flags);
+ elapsed = pit_cnt;
+ t = at91_sys_read(AT91_PIT_PIIR);
+ raw_local_irq_restore(flags);
- return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
+ elapsed += PIT_PICNT(t) * pit_cycle;
+ elapsed += PIT_CPIV(t);
+ return elapsed;
}
+static struct clocksource pit_clk = {
+ .name = "pit",
+ .rating = 175,
+ .read = read_pit_clk,
+ .shift = 20,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+/*
+ * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
+ */
+static void
+pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+ unsigned long flags;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ case CLOCK_EVT_MODE_RESUME:
+ /* update clocksource counter, then enable the IRQ */
+ raw_local_irq_save(flags);
+ pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+ | AT91_PIT_PITIEN);
+ raw_local_irq_restore(flags);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ BUG();
+ /* FALLTHROUGH */
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_UNUSED:
+ /* disable irq, leaving the clocksource active */
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+ break;
+ }
+}
+
+static struct clock_event_device pit_clkevt = {
+ .name = "pit",
+ .features = CLOCK_EVT_FEAT_PERIODIC,
+ .shift = 32,
+ .rating = 100,
+ .set_mode = pit_clkevt_mode,
+};
+
+
/*
* IRQ handler for the timer.
*/
-static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
{
- volatile long nr_ticks;
- if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
- write_seqlock(&xtime_lock);
+ /* The PIT interrupt may be disabled, and is shared */
+ if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
+ && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
+ unsigned nr_ticks;
- /* Get number to ticks performed before interrupt and clear PIT interrupt */
+ /* Get number of ticks performed before irq, and ack it */
nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
do {
- timer_tick();
+ pit_cnt += pit_cycle;
+ pit_clkevt.event_handler(&pit_clkevt);
nr_ticks--;
} while (nr_ticks);
- write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
- } else
- return IRQ_NONE; /* not handled */
+ }
+
+ return IRQ_NONE;
}
-static struct irqaction at91sam926x_timer_irq = {
- .name = "at91_tick",
- .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = at91sam926x_timer_interrupt
+static struct irqaction at91sam926x_pit_irq = {
+ .name = "pit",
+ .flags = IRQF_SHARED | IRQF_DISABLED
+ | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = at91sam926x_pit_interrupt
};
-void at91sam926x_timer_reset(void)
+static void at91sam926x_pit_reset(void)
{
- /* Disable timer */
+ /* Disable timer and irqs */
at91_sys_write(AT91_PIT_MR, 0);
- /* Clear any pending interrupts */
- (void) at91_sys_read(AT91_PIT_PIVR);
+ /* Clear any pending interrupts, wait for PIT to stop counting */
+ while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+ cpu_relax();
- /* Set Period Interval timer and enable its interrupt */
- at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
+ /* Start PIT but don't enable IRQ */
+ at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
}
/*
- * Set up timer interrupt.
+ * Set up both clocksource and clockevent support.
*/
-void __init at91sam926x_timer_init(void)
+static void __init at91sam926x_pit_init(void)
{
+ unsigned long pit_rate;
+ unsigned bits;
+
+ /* Use our actual MCK to figure out how many MCK/16 ticks per
+ * 1/HZ period (instead of a compile-time constant LATCH).
+ */
+ pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+ pit_cycle = (pit_rate + HZ/2) / HZ;
+ WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
+
/* Initialize and enable the timer */
- at91sam926x_timer_reset();
+ at91sam926x_pit_reset();
- /* Make IRQs happen for the system timer. */
- setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
+ /* Register clocksource. The high order bits of PIV are unused,
+ * so this isn't a 32-bit counter unless we get clockevent irqs.
+ */
+ pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
+ bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
+ pit_clk.mask = CLOCKSOURCE_MASK(bits);
+ clocksource_register(&pit_clk);
+
+ /* Set up and register clockevents and irq handler */
+ pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
+ pit_clkevt.cpumask = cpumask_of_cpu(0);
+ setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+ clockevents_register_device(&pit_clkevt);
}
-#ifdef CONFIG_PM
-static void at91sam926x_timer_suspend(void)
+static void at91sam926x_pit_suspend(void)
{
/* Disable timer */
at91_sys_write(AT91_PIT_MR, 0);
}
-#else
-#define at91sam926x_timer_suspend NULL
-#endif
struct sys_timer at91sam926x_timer = {
- .init = at91sam926x_timer_init,
- .offset = at91sam926x_gettimeoffset,
- .suspend = at91sam926x_timer_suspend,
- .resume = at91sam926x_timer_reset,
+ .init = at91sam926x_pit_init,
+ .suspend = at91sam926x_pit_suspend,
+ .resume = at91sam926x_pit_reset,
};
-
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