I have AT91SAM7X512 with DP83848 board. But I got the problem with clock after power on. Please tell me some hints how to debug that. Because of the clock DP83848 Phy is not latching the configuration pins.

Hi

I am not sure exactly what you mean by the clock problem but there are some details about latching the PHY mode correctly at the followng link:

http://www.utasker.com/forum/index.php?topic=161.0

Regards

Mark

http://www.uTasker.com

Hi folks, there seems to be a fair amount of shared experience on PHY setup on this thread..
Here is my problem.. I have removed the DM9161AEP on my AT91SAM7X-EK and replaced it with a DM9161EP.
A few changes to the code to add the different PHYID code for DM9161EP gets it running as before... Only there is nothing I can do get the 'LINK STATUS' flag to indicate the Ethernet is connected. Most code (uIP LwIP etc..) relies on polling this bit (Address 1, bit 2) in the BMSR (Basic mode status register) to indicate there is something plugged in before proceeding. In this case of the DM9161EP - there is nothing I can do to get this it to set..

Download the same code on a AT91SAM7X-EK with the original DM9161AEP - and it works no problem.

At this stage I have tried countless combinations of MII register settings and nothing seems to get it to work. The funny thing is nearly all the register settings I use for the DM9161AEP work fine.. there is very little I can do to stop this baby springing into life and setting the ‘LINK STATUS’ flag..
I guess my question is why is the DM9161EP being so fussy!! Is there an errata that I am not aware of? Do you know of a product that uses the DM9161EP - and DM9161AEP - what is the difference?? I have looked at the datasheet to the point of desperation and despair!

Before you say “why don’t you use DM9161AEP and forget about the DM9161EP”, it’s because I need to support 100BASE-FX, and only the DM9161EP supports it. If I can’t fix this problem.. my optical Ethernet board has no chance of working..

I did some initial investigation.. which may hint at the route I have taken so far (and discounted..)
----
Keywords:
Using the 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver. Fiber Fibre Ethernet 100BASE-FX 100FX 1310nm

OK, found out what you need to get this working..
As always, the devil is in the datasheet – and this is what he told me… Firstly, From Datasheet DM9161-DS-F05 (September 10, 2008) Section 8, MII Register Description, Address 2 & 3. ‘EP’ and ‘AEP’
chips have different IDs. Does your driver check them against a list of ‘supported’ IDs?
Then, Address 16, FX/FX Select. The default is TX – For fibre, you need to clear this bit.
Lastly, and this is a pain, many of the pins of the DAVICOM are read as inputs on power-up. See Section 5, “LI: Latch input when power-up /reset”. The state of these pins will overwrite the contents of the “MII Register Description” – So, if you have slightly changed the circuit and put a small biasing voltage on one of the inputs that may have been open circuit before, it will change the contents of the corresponding MII Register!!!!!. This happens on the Atmel board to the Address 0, bit 10: Isolate flag. The SAM7_MAC.c always overwrites this register…. BUT there are 7 OTHER registers that can get overwritten in this way!! The SAM7_MAC.c code does not set these to a ‘known’ state.. It relies on the ‘Latch input on power-up’, which caught me out.
All registers that are affected are listed in Table 5.1 (column ‘I/O’, those marked with ‘LI’). Read the description of the registers that is affected on power-up. Make sure you overwrite the contents of these registers as part of you PHY init routine - to be safe, simply overwrite all writable values. See Section 8.14, it tells you what these 8 register (groups) are set to when you power up.
When you are done, you may wish to reset the ‘PHY state machine’ (Address 16, bit 3).
Jon Newcomb
http://www.jnewcomb.com/cv/

OK.. now I have given up. I have assembled everything found so far - and now I'm going to crawl into a hole and hope the problem goes away.

Description of the problem. Our final board uses the DM9161EP running fibre, but we have a problem setting up the DM9161EP.
To help investigate the problem I have the following setup:
I have two AT91SAM7X-EK evaluation boards; The only difference is one has the original DM9161AEP PHY chip, and another has the DM9161EP version of the chip.
I changed the IAR example to allow the different PHYID (MII address 2 & 3) to be recognised.
This code was tested on both boards. The DM9161AEP works without problems, but the board with the DM9161EP does not work.
The only difference between these who setups is the PHY chips..

To help me understand the problem I have captured the MII registers after a reset / write configuration (left column), then after 5 seconds (right hand column) This is what I see

Board with origonal DM9161AEP (Working)
MII Power On After 5 Seconds
[0] 0x00001000 0x00003100
[1] 0x00007809 0x0000782D <- ‘Link Status’ found
[2] 0x00000181 0x00000181
[3] 0x0000B8A0 0x0000B8A0
[4] 0x00000101 0x00000101
[5] 0x00000000 0x000045E1
[6] 0x00000000 0x00000001
[7] 0x00000000 0x00000000
[8] 0x00000000 0x00000000
[9] 0x00000000 0x00000000
[10] 0x00000000 0x00000000
[11] 0x00000000 0x00000000
[12] 0x00000000 0x00000000
[13] 0x00000000 0x00000000
[14] 0x00000000 0x00000000
[15] 0x00000000 0x00000000
[16] 0x00000400 0x00000400
[17] 0x0000F3F0 0x000083F8 <- Auto Neg. Complete
[18] 0x00005800 0x00005800
[19] 0x00000000 0x00000000
[20] 0x00000000 0x00000000
[21] 0x00001F00 0x00001F00
[22] 0x00000000 0x00000000
[23] 0x00000000 0x00000000
[24] 0x0000D6FF 0x000006FF
As you can see, after 5 seconds, the auto negotiation is complete (address 17.3-17.0) and link sense is found (address 1.2)
Everything is working as expected.

Next the same code is run on the board that has the DM9161EP version of the chip. This is what I see.
Board with DM9161EP (Not Working)
MII Power On After 5 Seconds
[0] 0x00001000 0x00001000
[1] 0x00007809 0x00007809 <- ‘Link status’ not found
[2] 0x00000181 0x00000181
[3] 0x0000B881 0x0000B881
[4] 0x00000101 0x00000101
[5] 0x00000000 0x000045E1
[6] 0x00000000 0x00000001
[T] 0x00000000 0x00000000
[8] 0x00000000 0x00000000
[9] 0x00000000 0x00000000
[10] 0x00000000 0x00000000
[11] 0x00000000 0x00000000
[12] 0x00000000 0x00000000
[13] 0x00000000 0x00000000
[14] 0x00000000 0x00000000
[15] 0x00000000 0x00000000
[16] 0x00000400 0x00000400
[17] 0x0000F1F0 0x0000F1F4 <- Auto Neg. ‘Consistency Match’
[18] 0x00005800 0x00005800
[19] 0x00000000 0x00000000
[20] 0x00000000 0x00000000
[21] 0x00000F00 0x00000F00
[22] 0x00000000 0x00000000
[23] 0x00000000 0x00000000
[24] 0x000026FF 0x000036FF
I can see the auto negotiation is set to ‘Consistency Match’, not ‘Auto Neg complete’ (address 17.3-17.0) and the link sense is not found. (address 1.2)
This means the MAC driver exits as it has no link status – it will then force a reset cycle and the whole process starts again. No Ethernet connection.

I am really perplex as to what the difference is that could cause this problem. I have changed combinations to the configuration registers for many different startup configurations – my only conclusion is that the DM9161AEP version of the chip seems to work with nearly all combinations of MII register settings, it is difficult to stop it working!! Sadly, none of these combinations of settings work on the board that has the DM9161EP PHY.

Few points to note:
When powered up, I overwrite the control register (Addr0), Auto Neg Advertise (Addr4), Config (Addr16) with known values. I do not rely on the configuration set by the ‘Latch input when powerup / reset’.
A few of the reserved bits are set on the DM9161AEP version. I’m not really sure why.
If I find out a solution, I will post here.. if you have any suggestions.. please post or contact me.
Jon.
http://www.jnewcomb.com/cv/

May be it's an external hardware / wiring issue.

What's pin 45 (SD) connected to? The 100BASE-FX stuff uses PECL, pin 45 controls the RX/TX signalling voltages. It's a NC on the AE(P) parts.

Pin 39 DVDD, vs DISMDIX

Pins 1,2,9 AVDD, vs AVDDR,AVDDR,AVDDT

While not exactly the right part, the following might be instructive for FX attachment.
http://www.davicom.com.tw/userfile/2424 ... ircuit.pdf

http://www.dacomwest.de/pdf/dm9161_seri ... change.pdf

Could be a cabling issue.

The DM9161AEP part has Auto-MDIX (automatic medium-dependent interface crossover).

IOW: It detects the cable type (straight through or crossover) and makes the appropriate changes.

The DM9161EP part does not have this...

CptTitanic, very good points.
pin 39 in the DM9161EP is DVDD input.
I have connected together 1,2,9 to DVDD (Via an inductor with appropriate caps)
Also, and this is what got me.. the centre tap on the RX transformer is NOT connected to AVCC. The TX centre tap is..

Found this link too.
http://forum.embedded-projects.net/viewtopic.php?id=276

All this helped me get my AT91SAM7X-EK with the DM9161EP / DM9161E PHY working again.. thanks.

Just so you know, after I got it working I tried a normal and a crossover cable - They both worked. It is my guess the router took care of all that for me..
____________
So, I then ported across this new found knowledge onto our 100BASE-FX fibre board - using the AVAGO AFBR5803Z / AFBR 5803Z
and hey presto, it did not work. Lots of trial and error later... This is what I did to get it to work..

Turn off Auto negotiation, Set the speed to 100Mbs, Set to Full Duplex mode. See 'Basic Mode CR', (MII Address 0)
Advertise only TX_FDX (100 Mbs / full duplex) and IEEE802.3 CSMA/CD Selector. See 'ANAR', (MII Address 4)
Then Bypass the scrambler/descrambler and verify the TX flag is clear See 'DSCR', (Address 16)

This is a snip of code that configures the registers..
vWritePHY (AT91C_PHY_ADDR, MII_BMCR, (BMCR_FULLDPLX | BMCR_SPEED100 ) );
vWritePHY (AT91C_PHY_ADDR, MII_ADVERTISE, (ADVERTISE_100FULL | ADVERTISE_CSMA));
vWritePHY (AT91C_PHY_ADDR, MII_DSCR, ( DSCR_SCRAMB ));

This is what the MII registers looked like once the link sense was found..
[0] 0x00002100
[1] 0x0000780D
[2] 0x00000181
[3] 0x0000B881
[4] 0x00000101
[5] 0x00000000
[6] 0x00000000
[T] 0x00000000
[8] 0x00000000
[9] 0x00000000
[10] 0x00000000
[11] 0x00000000
[12] 0x00000000
[13] 0x00000000
[14] 0x00000000
[15] 0x00000000
[16] 0x00004000
[17] Ox0000F1FO
[18] 0x00005800
[19] 0x00000000
[20] 0x00000000
[21] 0x00000F00
[22] 0x00000000
[23] 0x00000000
[24] Ox000026FF

After this my 100BASE-FX works a treat!!

FYI, this is what my code for the DM9161AEP / DM9161AE using wired ethernet looks like..
vWritePHY (AT91C_PHY_ADDR, MII_BMCR, (BMCR_ANENABLE) );
vWritePHY (AT91C_PHY_ADDR, MII_ADVERTISE, (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF | ADVERTISE_CSMA));
vWritePHY (AT91C_PHY_ADDR, MII_DSCR, ( DSCR_TX ));
...
Hope you find this info useful folks.. it was hard earned!
Jon Newcomb
http://www.jnewcomb.com/cv/