Hi all,

I am developing an application using (AT91Sam7s64) that has a requirement to switch from a fast PLL speed to a slow one for power saving. Out of 150 units 4 of then reset continuously (watchdog reset caused by undefined instructions).

I thought I was being careful and following the datasheet but I must be doing something wrong!

speeding the PLL clock up I.......

disabled_interrupts();
AT91C_BASE_PMC->PMC_PLLR = 0x00191c05; // Set PLL output to 95.8464Mhz
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000004)); // Wait for PLL to stabilise
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000008)); // Wait for master clock to be ready
AT91C_BASE_PMC->PMC_MCKR &= 0xffffffef; // Set PLL/2 = 47.923200MHz
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000008)); // Wait for master clock to be ready
AT91C_BASE_PMC->PMC_MCKR |= 0x00000003; // Select PLL
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000008));

and slowing it down I....

disabled_interrupts();
AT91C_BASE_PMC->PMC_PLLR = 0x003f1c0a; // Set PLL output to 117.964800Mhz
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000004)); // Wait for PLL to stabilise
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000008)); // Wait for master clock to be ready
AT91C_BASE_PMC->PMC_MCKR |= 0x00000014; // Set PLL/32 = 3.6864MHz
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000008)); // Wait for master clock to be ready AT91C_BASE_PMC->PMC_MCKR |= 0x00000003; // Select PLL
while(!(AT91C_BASE_PMC->PMC_SR & 0x00000008));

The only method I have come across that seems to fix this bug is to enable the MCKRDY interrupt! This seems very unlikely to be the real solution as am polling MCKRDY but I'm wondering if its a clue.

I have also tried setting PRES and CSS seperately but to no avail.

Does anyone have any hints or tips for me?

Help!

swilson

Hello,

why not switch to slow or main (oscilator) clock first, then change parameters for pll, wait for pll to stabilize and then switch back?


Also note that there is a speed range where the flash does not work properly. If this range is touched while changing the speed with the pll I expect an undefined error.

MCK: Limited Master Clock Frequency Ranges
If the Flash is operating with ... wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than ... MHz.


Greetings,
Thorsten

Hi Thorstenw,

Thanks for the reply.

Interestingly I do use one wait state and I'm setting my MCK to 3.6864MHz. So I should expect a data abort??

However if i set MCK within range (I have tried 1.8432Mhz & 29.4912MHz) I still have the same problem.

Sarah