Hello,

How do I syncronise receiver and tranmitter shift registers to start at first bit of data when NCS0- goes low?

I have problems with the SPI slave mode.
I am not able to syncronise first data bit reveiced with first clock cycle after NCS0 goes low.

I can get the AT91C_SPI_RDRF irq early by 1, 2, 3 or even 4 SPI clock cycles after NCS0 goes low. The data received is then also bit offset but this number of cycles.

Don't worry, I have SPI set correctly for phase,cpol and bit = 8. too easy.

Datasheet states that serializer starts operating when NCS0 goes low.
Block diagram for slave mode does NOT show how serializer is reset to shift out first bit.

The Atmel SPI app note is not relevant to this. Too basic
No simple SPI sample SLAVE code could be found in EK CD and at the Atmel links provided in this forum earlier (a few years ago).

There is no irq possible on NCS0 going low so this cannot be used to synchronise either.

Kind regards
Bernt