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 Post subject: MCK speed and flash wait cycle
PostPosted: Mon Mar 08, 2010 8:20 pm 
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Joined: Tue Jun 14, 2005 7:49 am
Posts: 33
I set AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_0FWS | FMCN ;

and my MCK is 48MHz, the chip runs fine. The document says 0 wait state only support up to 30MHz. Why am I running fine?
Does AT91C_MC_FWS_1FWS slow down the speed of execution? How much does it slow down?


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 Post subject: Re: MCK speed and flash wait cycle
PostPosted: Sat Sep 25, 2010 2:44 am 
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Joined: Fri Sep 24, 2010 10:00 pm
Posts: 3
I am a newbie to firmware, but I believe you've just gotten lucky (unless you're using a chip with really fast flash, i.e., supports a zero wait state). As I understand it, the flash wait states are to ensure the signal voltage has stabilized before the result is read by the CPU.

So, it may work for your particular chip. At its current temperature. The next chip you order may not have the same characteristics.

A flash wait state of 1 is not a terribly long delay; it's explained in detail in the CPU's datasheet. Most CPUs that execute out of flash have an instruction prefetch as well as a read cache for the flash, which negates the FWS in most situations.

-Steve


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