I'm using the pulse width modulator (PWM) on a SAM7S to provide control signals to an external circuit. I'm using all four channels and I need to have them start at precisely the same time. Normally, this could be easily done by simply enabling all the channels at once, but there's an additional complication.

Two of the channels have fairly short periods and require fine control of the duty cycle. Therefore, they run at the processor clock frequency (MCK). The other two channels have fairly long periods (approximately 480,000/MCK). Due to the 16 bit size of the PWM counters, these two channels have to run on a slower clock - I selected MCK/8. When I enable all the channels at one time, the two channels running at MCK start on the next processor clock tick. But the two channels running on MCK/8 start from 1 to 8 clock ticks later. This was sort of expected because there's no way to reset the modulo N counter that controls the MCK/8 clock source.

As an experiment, I tried switching to using CLKA and CLKB (with divisors set to 1 and 8 respectively) with similar results. I then tried another variation - I first disabled CLKA and CLKB by setting their divisors to zero. Next, I enabled all four channels and finally I enabled CLKA and CLKB by setting the proper divisors. Surprisingly, this works a large percentage of the time, but still fails on occasion.

I realize that I'm probably trying to do something that was not part of the PWM design specs. It seems that I need a way to either reset the modulo N counters or the CLKA/CLKB dividers. Has anyone else tried to do this or does anyone have any ideas of something to try?

Thanks for any help.

I have never tried this but...

Have you tried disabling the peripherial clock for the PWM in the PMC?

something like:
1) disable PWM peripherial clock in PMC
2) setup PWM registers
3) enable PWM peripherial clock in PWM

That was an interesting idea. I tried your technique and some variations of it. At first, it looked promising, but eventually I discovered that the problem was still there.

This has been a real pain in the neck problem. Just when it looks like I might have a solution, a small change to an unrelated piece of code will seem to disturb the delicate timing and cause the symptoms to reappear.

The quest continues....

Have you tried adding a reset of the peripherials in the RSTC?

Granted this could be ugly, but this (should?) reset the internal counters for the PWM.

Of course the other option is HW...

Unfortunately, that's not an option. There are too many other peripherals in use (e.g., USB and serial port). I need to stop, reconfigure, and restart the PWM about once a minute. It would be really tough to synchronize that with other activities.

It's beginning to look like some external hardware assistance is going to be required.

Well I'm about out of ideas...

If you are able to share... what are you interfacing to?

I'm not allowed to provide much detail. One of the PWM channels provides a clock to an external ADC. The frequency of that signal is between roughly 8MHz (6 CPU clock cycles) and 16MHz (3 CPU clock cycles). The other 3 PWM channels control other portions of the external circuit and it's important that they do not change at the same time that an ADC sample occurs. And that's why all the channels must be exactly synchronized - I've got a very narrow time window to hit.

Hmm. Of course this brings more questions but...

Have you tried switching the two slow channels to PIO lines and controlling them via a timer or using an interrupt on one of the PWM channels to drive these?

You can't synchronize the start of the timers with the start of the PWM - plus I've already got two timers in use. And software control is too unpredictable - I can't afford to be off by even a single processor clock tick.

I think that we've beat this horse to death.

Agreed. Good luck with your project!