Why does SSC TD Output delay 3 bits?

shofar · **Joined:** Thu Dec 04, 2008 3:21 am **Posts:** 1

AT91SAM7S64 SPI Peripheral is set to function as SPI master,so I have to make ssc function as spi slave.

And I use two dma to transmit and receive data.
Both TD and RD is set to Continuous mode.STTDLY is set to 0.
Clock is fed to TK,RK uses TK.
NO TF and RF.

void init_ssc()
{
pSSC->SSC_CR = 0x00008202; /* reset ssc */

pSSC->SSC_IDR = 0x00000fff; /* Disable all interrupt */
pSSC->SSC_CMR = 0x00000000; /* MCK/2/100 */
/* TK Clock signal, None Clock Output */
/* CKG = 0x0, CKI = 0x1, CKO = 0x0, CKS = 0x1 */
pSSC->SSC_RCMR = 0x00000021; /* CKS use TK Clock signal */
/* DATLEN = 7, LOOP = 0, MSBF = 0 */
pSSC->SSC_RFMR = 0x00000007; /* 8bit */
pSSC->SSC_TCMR = 0x00000002; /* CKS use TK Pin */
pSSC->SSC_TFMR = 0x00000007; /* MSB, 8bit */

pSSC->SSC_CR = 0x00000101; /* SSC RX TX enable */

}

void SSC_dma_send(unsigned char *data, unsigned long count)
{
pPDC_SSC->PDC_TPR = (unsigned long)data;
pPDC_SSC->PDC_TCR = count;
pPDC_SSC->PDC_PTCR = 0x101;
}
void SSC_dma_read(unsigned char *data, unsigned long count)
{
pPDC_SSC->PDC_RPR = (unsigned long)data;
pPDC_SSC->PDC_RCR = count;
}

I connect RD to TD for test purpose.
I call them as follows:

SSC_dma_read(pRXBuffer,length);
SSC_dma_send(pTXBuffer,length);
then I generate clock to TK pin.
The receive is OK,but the transmit delays 3 bits.(If SSC_THR is set 0x01,the receiver will receive 0x08.Three bits delay).
Why?
Can anyone help me?

raaki009 · **Joined:** Thu Mar 05, 2009 9:31 am **Posts:** 5

Hi Shofar,

i am experiencing similar kind of problem with SSC. Do you find any interesting news about this behavior?

thanks and regards,
raaki

Vengin · **Joined:** Wed Aug 04, 2010 2:45 pm **Posts:** 1

Hello there.
I've encountered the same problem on my AT91SAM7X256 SSC working as SPI Slave via SSC. The output data is 3 bits delayed. But here's a kind of a workaround if you wish. The main idea is to add a 5-bit delay (using SSC STTDLY) and to ignore that unnecessary byte on the SPI Master side. Maybe my information will be useful.

And here is the code to configure SSC Transmit Clock Mode Register (SSC_TCMR):

Code:

   //Configure Transmitter
   AT91C_BASE_SSC->SSC_TCMR =
      AT91C_SSC_CKS_TK                          | //TK <= RK Pin
      AT91C_SSC_CKO_NONE                        | //Clock Output Mode: None RK pin: Input-only
      (AT91C_SSC_CKI & (0x0 << 5))              | //TD/TF Shifted out on Falling(0)/Rising(1) edge
      AT91C_SSC_CKG_NONE                        | //No Clock Gating
      AT91C_SSC_START_CONTINOUS                 | //Continuous
      //AT91C_SSC_START_TX                        | //Sync with RX
      SSC_STTDLY(5)                             |//adding 5-Bit Delay to eliminate internal 3-Bit delay
      (AT91C_SSC_PERIOD & (0x00 << 24))         ; //No Period

Why does SSC TD Output delay 3 bits?

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