Sorry if this has an obvious answer; I'm an experienced programmer but new to firmware.

A EE on my team has designed a board with an FPGA that gives me data at regular intervals. When the Data Ready line goes active, I need to read in 122 bytes in ~2ms. He's hooked up 8 data lines and a clock line instead of going over a standard bus like SPI or USART.

I know I can do this just by manually setting and clearing the clock line, but we were talking yesterday about alternative solutions and I'd like to get some opinions from experienced firmware developers.

Environment: AT91SAM7X512 chip in a custom board, with Rowley (gcc) toolset and FreeRTOS.

The FPGA clock line is hooked to the pin multiplexed as PB29/PCK1/PWM2/AD2. So, I know I can manually drive it as PB29 with the appropriate (spin) delays.

The question is: can I set up this pin to cycle automatically based on MCK and give me interrupts to read the data? I could then set up a DMA sort of interface.

I can program PCK1 to cycle the clock automatically, but when I looked at the PMC documentation there didn't seem to be a way to get an edge-triggered interrupt from this. So I don't *think* that's a viable option.

I'm not familiar with PWM (other than having heard the term). I read the docs and it looks like I can set up an automatic cycling similar to a PCK, but the docs note that they do not recommend edge-triggered interrupts with PWM. So I'm thinking that isn't viable either.

With an MCK of 47.9232MHz and a EE who would like the transfer speed at about 20MHz (though it *could* be much slower), I'm also wondering if an interrupt-based solution would be worth persuing at all.

Thanks,
-Steve