Hi. My name is Nicolás. I'm new to the community. I'm from Argentina and work as Design and Development Engineer.

Ever since I work in the company where I'm employed, there is a System developing around a SAM7A3 uC. It consists of a very complex, custom made RTOS written in C/C++ in IAR.

The RTOS has two, I could say, blocks: a HAL (drivers implementation) and an application Framework (interface between drivers and application, data managing).

There was a major hardware redesign, that led to a RTOS reimplementation.

The drivers had to be rewritten, but the basic ISR didn't. We use two time basis: A 50uS PIT and a 2mS TMR0

Everything seemed to work fine, but, sometimes, without any reason for me to understand, the PIT interruption ceases to work.

I tried many different things, but I couldn't get a conclusion.

For more information, the PIT is configured as FIQ, the TMR0 as a normal IRQ, and the PIT isn't disabled anywhere in the code.

UPDATE:

I'm runing new tests to find out if it's really only the PIT that is disabled or any interruption source. I hope somebody had a similar experience and could lend me a hand.

Consider edge vs level sensitive interrupts, and whether things are cleared appropriately. Consider the run-time of the FIQ, are you performing a task(s) that exceeds the duty cycle of the interrupt. The FIQ is an NMI equivalent, do something simple (increment counter), and leave. A 20 KHz interrupt rate seems kind of high, gives you about 1500 machine cycles optimistically.