Hi
There was a new PLL restriction introduced in newer SAM7X parts (I don't know about the SAM7S parts but presumably similar). Original PLL configuration had difficulty when used with newer chips and had to be modified to respect the details in the newest data sheet (compared to the original data sheet there are changes which are not listed in the documentation history).
After carefully following the recommendation, the PLL could again be set reliably:
while (!(PMC_SR & PLL_LOCK)) {} // wait for PLL lock before continuing
PMC_MCKR = CLK_PRES; // {74} first program the prescale and wait for ready
while (!(PMC_SR & MCKRDY)) {} // {74} wait for the master clock status to indicate ready
PMC_MCKR = (SELECT_PLL | CLK_PRES); // finally set the master clock to half the PLL value
while (!(PMC_SR & MCKRDY)) {} // {74} wait for the master clock status to indicate ready
The lines marked with {74} had to be added. Originally the prescaler and master clock settings could be programmed in one go but that changed at some time and they need to be programmed separately.
Regards
Mark
www.uTasker.com