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 Post subject: Another AT91SAM7S256 Rev C issue with the clock
PostPosted: Tue Jun 14, 2011 9:03 pm 
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Joined: Fri Jun 12, 2009 1:54 pm
Posts: 17
I just finished pulling my hair out on another issue we had when moving to the Rev C chips. We are using a custom bootloader that will do something like this upon reset:

Reset()
{
IF SomeFlashLocation[x] == MAGIC_NUMBER Then goto ApplicationStartupCode();

// if not, we are in firmware update mode and do the following:
LowLevelInit();
Copy Bootloader to RAM
Goto Bootloader() in RAM
}

LowLevelInit()
{
Initialize Main Oscillator
Setup PLL
Setup Master Clock
}

Bootloader()
{
flash some LED to indicate that we are ready to download firmware
}


This worked fine with the Rev B chip, but the new Rev C chip will not get to the flashing LED. It stalls prior to that. After narrowing it down I came to this conclusion:

In the LowLevelInit function, I am setting up the Master Clock like this:

while (!(PMC_INTERRUPT_STATUS & 4));

// wait for the master clock if it was already initialized
while (!(PMC_INTERRUPT_STATUS & 8));

// switch to slow clock + prescaler
PMC_MASTER_CLK = PMC_CLK_SELECTION_SLOW_CLOCK | PMC_CLK_PRESCALE_DIV_2;
while (!(PMC_INTERRUPT_STATUS & 8));

// switch to fast clock + prescaler
PMC_MASTER_CLK |= PMC_CLK_SELECTION_PLL_CLOCK;
while (!(PMC_INTERRUPT_STATUS & 8));


I don't see whats wrong with that, the application code does the exact same thing and it works fine. The code stalls on the last two lines, where the master clock is set to be a fast clock. If I comment those out, continuing to run a slow clock, it will actually work (very slow of course). Now, if I move the master clock setup to be done in RAM (Bootloader() function), all works perfectly fine.


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 Post subject: Re: Another AT91SAM7S256 Rev C issue with the clock
PostPosted: Tue Jun 14, 2011 9:16 pm 
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Joined: Fri Jun 12, 2009 1:54 pm
Posts: 17
I figured out what happened: I forgot to set the flash wait states before setting the main clock to be fast. I did set them in the bootloader and application code. Apparently the Rev B chip tolerated this, the Rev C chip fails. Setting the wait states appropriately solved the issue.


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