at91sam7x256 watchdog issue

hulud · **Posted:** Sat Feb 24, 2007 1:41 am

Hi,
i'm working on a AT91SAM7X-EK development board, and i'm trying to
figure out if the normal at91 watchdog behavior can be changed or
workarounded because:

"The Watchdog Mode Register (WDT_MR) can be written only once. Only a
processor reset
resets it. Writing the WDT_MR register reloads the timer with the
newly programmed mode
parameters."

due to this feature, if i disable watchdog on start up, i'm not able
to turn in on anymore until the next reset.
What i want to do is disable watchdog on startup, and then turn it on
later (on a custom received can message).
but the as the datasheet says, after writing to the register to
disable watchdog, the following command to turn it on is ignored.
what can i do? is there a way to workaround this (imho stupid)
behavior?

Andrea

gerhardf · **Joined:** Thu Dec 02, 2004 2:28 pm **Posts:** 454

hello andrea,
after reset the watchdog is disabled by default. so let it in this state until the can message is disabled.

btw: this "stupid" behaviour is implemented in early every Âµc with watchdog.

regards
gerhard

hulud · **Posted:** Wed Feb 28, 2007 9:37 am

the datasheet says that:
"This means that a default Watchdog is running at reset, i.e., at power-up."
at boot watchdog is set to 16s.
any way to workaround this?

gerhardf · **Joined:** Thu Dec 02, 2004 2:28 pm **Posts:** 454

hulud wrote:

the datasheet says that:
"This means that a default Watchdog is running at reset, i.e., at power-up."
at boot watchdog is set to 16s.

you are right, sorry for the mistake!

hulud wrote:

any way to workaround this?

let the watchdog generate an interrupt instead of a reset.
and decide in the interrupt service routine if the watchdog should be already active or not (depending on the received can message).

regards
gerhard

dumarjo · **Posted:** Wed Mar 14, 2007 3:21 pm

how do you reset in this interrupt ?

jonathan

seadog · **Posted:** Mon Mar 19, 2007 4:12 pm

Code:

// pointer to microcontroller register
typedef volatile unsigned int * reg; 

// (RSTC) Reset Controller Control Register
#define RSTC_CR (*((reg) 0xFFFFFD00)) 

// key field
#define RSTC_KEY(x)     ((unsigned int)(x) << 24) 

// if key correct asserts NRST I/O pin
#define RSTC_CR_EXTRST  ((unsigned int)1 << 3) 

// if key correct resets peripherals
#define RSTC_CR_PERRST  ((unsigned int)1 << 2) 

// if key correct resets processor
#define RSTC_CR_PROCRST ((unsigned int)1 << 0) 

// put the below line in your ISR where you want the RESET...
RSTC_CR = RSTC_CR_PROCRST | RSTC_CR_PERRST | RSTC_KEY(0xA5);

hulud · **Posted:** Tue Mar 20, 2007 2:53 pm

i'm trying to set watchdog to call an interrupt instead of a reset with:

Code:

AT91C_BASE_WDTC->WDTC_WDMR = WDTC_COUNT | (WDTC_COUNT << 16) | AT91C_WDTC_WDFIEN;

but i can't find in my at91samyx256.h header file the id of wdt, in some examples i find that is used AT91C_ID_SYS for wdt interrupt, is this correct?
i'm using this interrupt for PIT timer, do i have to set it again? or just handle in the interrupt routine who call the interrupt?

seadog · **Posted:** Tue Mar 20, 2007 4:00 pm

Hulud,

In my opinion, the datasheet doesn't make the answer to your question very obvious or easy to find. If you look at the top-left corner of figure 9.1 there's a 6 input OR gate that shows the sources of interrupts that can generate a system interrupt. So, the answer to your question is YES, it is the "system interrupt" that processes the watchdog timer interrupt request. That's where you can read the watchdog timer status register to see if a watchdog timer timeout occurred, and handle it however you'd like to.

Good luck...
Seadog.

hulud · **Posted:** Tue Mar 20, 2007 4:07 pm

thank you seadog, now things turn clear.

dumarjo · **Posted:** Tue Mar 20, 2007 11:18 pm

thank you for this info !!!

regards

Jonathan

Ancaritha · **Joined:** Wed Jun 07, 2006 10:52 pm **Posts:** 60

Alrighty, I know this thread is about 2 years old, but it touches on exactly what I'm doing...

Skipping the long explanation, I need to capture the watchdog interrupt... but I can't seem to get it right.

I'm enabling the WDT with:

Code:

AT91C_BASE_WDTC->WDTC_WDMR = 0xCF | (0xCF << 16) | AT91C_WDTC_WDFIEN | AT91C_WDTC_WDDBGHLT | AT91C_WDTC_WDIDLEHLT;

When our system crashes and the watchdog would normally reset it... it just hangs. We're already configured to catch the system interrupt, as we use the PIT (and were previously using the dbgu). Inside the interrupt I'm checking the status register of the Watchdog:

Code:

U32 nWatchdogStatus = AT91C_BASE_WDTC->WDTC_WDSR;

if (nWatchdogStatus)
{
   // put the below line in your ISR where you want the RESET...
   RSTC_CR = RSTC_CR_PROCRST | RSTC_CR_PERRST | RSTC_KEY(0xA5);
}

but it never seems to actually hit the reset command (which I stole from this thread, thanks!).

If I put the watchdog config back to the previous way:

Code:

AT91C_BASE_WDTC->WDTC_WDMR = 0xCF | (0xCF << 16) | AT91C_WDTC_WDRSTEN | AT91C_WDTC_WDDBGHLT | AT91C_WDTC_WDIDLEHLT;

The system resets just like it should.

I'm setting up the AIC to handle the interrupt (and setting up the PMC) below.

Code:

// open interrupt
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SYS, INTERRUPT_PRIORITY_SEVEN, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, InterruptServicer::Interrupt_ID_SYS);

// Enable Peripheral clock in PMC for  PITC
AT91F_PITC_CfgPMC();

// Enable AIC to catch the interrupt
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);

// Enable Interrupts
AT91F_PITEnableInt(AT91C_BASE_PITC);

This is the only interrupt in the system set at priority seven.

Anyone have any idea what I'm doing wrong? Any help would be greatly appreciated, thank you.

at91sam7x256 watchdog issue

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