I was looking for the max clock speed for the SSC in the AT91SAM7S64 data sheet. I didn't find a number anywhere, but there are two sentences at the end of page 317 that seem to give two different values for this max speed. One says the max speed is MCK / 2. The other says the input clock on TK/RK must be "stable" for two clock periods, which I interpret as two high and two low or MCK / 4. I would quote it all directly, but I can't copy from the data sheet (*%$# copy locking).

So if my MCLK is running at 48 MHz, what is the max clock rate I can apply to TK/RK of the SSC? What if I am using the internal clock and routing it to the outside via TK/RK, what is the max SSC clock speed?

Just as a suggestion, I find the Clock Generator and Power Management Controller sections of the data sheet to be a bit lacking in clarity on what connects to what. I found figures 7 and 8 on pages 19 and 20 to be helpful, but they should be added to the other sections as well. I shouldn't have to search through the document to find them.

Finally, if I am reading the data sheet correctly, the CPU clock can not be lowered without also lowering the peripheral clock since both are driven by MCK and the CPU clock can not be separately scaled down. Is that right?

So if I want to put the CPU in a low power state by slowing the clock, I can't use the SSC at the same max rate, correct?