From my understanding the JTAGSEL pin allows switching between ICE and JTAG operations.

I am using the AT91SAM7S-EK development kit with the IAR Workbench. Looking through Atmel's schematic at the JTAGSEL pin there is a connection to a pad and this connects to a VDDIO. But there is not a jumper on these empty pads so no voltage going to JTAGSEL. Since there is no jumper at JP18 so JTAGSEL is low. From the data sheet it says that embedded ICE mode is selected when JTAGSEL is low.

I am just trying to copy their design and do a prototype so I can program the chip. When would I ever want JTAGSEL to be high? (JTAG)

-Henk Visser

Hi henkvisser,
JTAG boundary scan can be used to set signal levels on desired pins. This is useful if you want test connections at production level without having a program inside the chip.

Lets say, you can not access the flash connected to CS0. There are some reasons for this.
- CS0 is not activated
- RD or WR signals are not driven
- shorts between two or more pins

JTAG boundary scan enables you to make a "step by step access" to this flash. So you can find which signal is wrong.

For a very easy explanation you can go to:

http://www.esatronik.de/english/jtag.php

Best regards,
Edi

Edi,

Thanks for the post! Very helpful!

-Henk