Hey all,

I am trying to hook up an FPGA to the SAM3U's External Bus Interface (EBI) and control it with the Static Memory Controller (SMC).

I have scoped the SMC signals going to the FPGA, please see the attached image.
In the attached image, you can see that the SAM3U adds approximately 5 extra cycles after reading 4 bytes from the EBI.

I have tried using DMA and a simple LDMIA instruction to read large amounts of data at once from the EBI, but the SAM3U always adds these additional 5 cycles after reading 4 bytes from the EBI.

Can anyone explain why this is, and how I can avoid this delay?
I would like to use no more than 4 cycles for reading a byte from the SMC, without additional delays.
Is this even possible?

Thanks in advance


Some more information:
NRD cycle time: 4 cycles,
NRD pulse: 3 cycles,
NRD setup: 0 cycles,
NRD hold: 1 cycle,

NCS setup: 0 cycles,
NCS pulse: 4 cycles,
NCS hold: 0 cycles.

The scope sample clock is the same as the SAM3U system clock.