I'm looking for some guidelines on the VDDOSC and VDDPLL decoupling rules, and, by looking at the AT91RM9200-DK project, I found a C-C-R discret component network on those analog pins. I do not understand the goal of this circuitry.
Some help will be helpful

Howdy July,

This C1-C2-R circuitry is very judicious:

Usually, some guys use (C1) 100nF decoupling capacitances on each power supply pins.
Other guys add a smaller capacitance (C2) in parallel with the first. The goal of this second smaller value capacitor is to correct the default of the previous capacitance (the serial intrinsic stray inductance).
The effect of this circuitry is, as result, to have a L-C2 second order system with its proper resonance frequency: In order to attenuate this resonance frequency, a resiostor can be connected in serial with the second capacitor. This is the goal of the resistor shown on the AT91RM9200-DK schematics.

I hope this helps.

I modeled the Murata GRM39-100NF-16V .1 uF used to decouple VDDOSC and VDDPLL based on the manufacturers S-parameters. The parasitic inductance is about 0.62nH and the series resistance is about .002 ohms. Theoretically there is little benefit to adding the extra 10 ohms and .1uF over 1MHz to 200 MHz. Outside that range, as the reactance exceeds 10 ohm, you get the benefit of another .1uF. I doubt this is relevant in practise.

However, Atmel may have found something in practise...

Spice sim attached in pdf...

Hello Jon,

I am in accordance with you.