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 Post subject: Unabe to reset the watchdog timer for AT91SAM7x256
PostPosted: Wed Dec 19, 2007 4:30 pm 
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Joined: Wed Dec 19, 2007 4:11 pm
Posts: 3
Location: Bangalore
Hi,

I am writing driver for Watchdog Timer of AT91SAM7x256.
I disabled the watchdog in Cstatrup_SAM.c file like -[/*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit(void)
{
unsigned char i;
/////////////////////////////////////////////////////////////////////////////////////////////////////
// EFC Init
/////////////////////////////////////////////////////////////////////////////////////////////////////
AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS; // 1 Wait State necessary to work at 48MHz

/////////////////////////////////////////////////////////////////////////////////////////////////////
// Init PMC Step 1. Enable Main Oscillator
// Main Oscillator startup time is board specific:
// Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms (0x40 for AT91C_CKGR_OSCOUNT field)
/////////////////////////////////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
// Wait Main Oscillator stabilization
while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));

/////////////////////////////////////////////////////////////////////////////////////////////////////
// Init PMC Step 2.
// Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz
// PLL Startup time depends on PLL RC filter: worst case is choosen
// UDP Clock (48,058MHz) is compliant with the Universal Serial Bus Specification (+/- 0.25% for full speed)
/////////////////////////////////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | AT91C_CKGR_OUT_0 | AT91C_CKGR_PLLCOUNT |
(AT91C_CKGR_MUL & (72 << 16)) | (AT91C_CKGR_DIV & 14);
// Wait for PLL stabilization
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
// Wait until the master clock is established for the case we already turn on the PLL
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );

/////////////////////////////////////////////////////////////////////////////////////////////////////
// Init PMC Step 3.
// Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
// The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
/////////////////////////////////////////////////////////////////////////////////////////////////////
AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );

AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
// Wait until the master clock is established
while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );

/////////////////////////////////////////////////////////////////////////////////////////////////////
// Disable Watchdog (write once register)
/////////////////////////////////////////////////////////////////////////////////////////////////////
[u]AT91F_WDTSetMode( AT91C_BASE_WDTC, 0x0fffb100);
//AT91C_BASE_WDTC->WDTC_WDMR = 0x0fffb100;
[/u]





/* AT91C_BASE_SYS->WDTC_WDMR = 0x0;*/

////////////////////////////////////////////////////////////////////////////////////////////////////
// Init AIC: assign corresponding handler for each interrupt source
/////////////////////////////////////////////////////////////////////////////////////////////////////
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
for (i = 1; i < 31; i++) {
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
}
AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
}]

after this i called a function init_wdt in main to reset the Watchdog like-[AT91C_BASE_SYS->WDTC_WDCR = 0xA5000001; /* watcdog Key- A5*/
AT91C_BASE_SYS->WDTC_WDMR = 0x0fff3100;/*to reload the watchdog*/
]
but the watchdog is not enabled .
Plz help me..

sandeep[/code]

_________________
sandeep kumar


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 Post subject:
PostPosted: Thu Dec 27, 2007 3:43 pm 
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Joined: Sat Dec 15, 2007 6:40 pm
Posts: 1
You only can dis- or enable the watchdog one time.

Normaly the watchdogtimer is enabled in the startup.

So when you want to disable the wdt in your main-funktion it´s to late and the watchdog will run the whole time.

Check your startup and you will be able to disable the wdt.


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