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 Post subject: AT91SAM9263-EK and SSC1 Issue
PostPosted: Wed Jul 16, 2008 1:57 am 
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Joined: Wed Jun 25, 2008 3:27 am
Posts: 10
Location: Seattle, WA, USA
Hi,

I am trying to set up an SSC controller on my evaluation board to be a PCM slave device. I had to make the following hardware modifications to get the SSC1 controller signals:

TK1: Break out signals on both sides of resistor "R9"
TF1: Break out signal on pin 12 of header "J24"
RD1: Break out signals on both sides of resistor "R122"
TD1: Break out signals on both sides of resistor "R7"

In all the cases above I didn't know which side of the resistor to get my signal from, hence, I used both sides. My goal is to use all the permutations above to determine the correct signals.

My problem is now in the device driver I have written for SSC1. I need the SSC to be configured as a slave device (ie clock and frame will be supplied to the SSC). To do so I have done the following:


Code:
AT91F_SSC_Configure( pSSC1, // pointer to SSC1 controler,
     0, //MAIN_CLOCK,
     0, // baud rate
     AT91C_SSC_CKS_TK +
     AT91C_SSC_START_HIGH_RF, // rx clock
     0x0F + AT91C_SSC_MSBF +
     AT91C_SSC_LOOP,                // rx mode
     AT91C_SSC_CKS_TK +
     AT91C_SSC_START_HIGH_RF +
     AT91C_SSC_CKI,                   // tx clock
     0x0F + AT91C_SSC_MSBF );    // tx mode

// Configure SSC interrupts
  AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC,
     AT91C_ID_SSC1,
     SSC_INTERRUPT_LEVEL,
     AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
     SSC_Handler);

  // Enable SSC1 interrupts in AIC
  AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SSC1);

  // Enable interrupts on completed receive buffer
  AT91F_SSC_EnableIt( AT91C_BASE_SSC1, AT91C_SSC_ENDRX);


I am trying to verify my configuration since I am not receiving any interrupts. The interrupt should assert when I receive a buffer (I chose loopback mode to force the interrupt to happen). I verified using an oscilloscope that a clock and framesync are being provided to the hardware, although I cannot say with certainty that the AT91SAM9263-EK is detecting the signals. This adds another complexity in the debugging.

Does anything look incorrect with the above or could someone provide any hints on how else to debug this issue?

Thanks very much.


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 Post subject:
PostPosted: Thu Jul 17, 2008 8:52 pm 
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Joined: Wed Jun 25, 2008 3:27 am
Posts: 10
Location: Seattle, WA, USA
SOLVED.....


For the benefit of others I have solved this issue and have details below:

There was one very important hardware modification required for the SSC. Although I specified the receive clock (RK1) source to be the transmit clock (TK1) in software, the framesync for the receiver still needs to come from somewhere. I had to physically connect the receive frame signal (RF1) to the transmit frame signal (TF1). The receive frame signal comes from either side of a 0 ohm resistor, R126, on the underside of the board.

Regards.


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