I am having problems with a new AT91SAM9263 design, and I wanted to see if anyone has insight.
I have built 10 protos, and on at least half of them, SAMBA gives an error reading “can’t initialize external RAM”. I’ve replaced RAM chips to avail, and the layout looks clean. This is largely the same design I've used on two other projects, which did not exhibit this problem.
The one difference between this project and the others is powerup sequencing. On the other boards, VDDBU is supplied by a battery, and the 3.3V and 1.2V supplies come up simultaneously, and reach their peak voltages within about 10-20 us. The new board has a lot of capacitance on the 3.3V rail, causing it to take several milliseconds to ramp up to its full voltage, and the 1.2V supply turns on when the 3.3V rail reaches about 2.3V. This was causing the processor to short out the 3.3V rail on some boards, so I added power sequencing to match the powerup behavior on the other projects. VDDBU is supplied by a supercap, diode-or’ed with the 3.3V supply through an LDO.
So I have addressed the powerup issue, but now i have the SDRAM problem with SAMBA. Some boards work fine (SDRAM access is normal), but on some of the boards, SAMBA can’t initialize the RAM. One other board is able to initialize, but can't reliably verify written contents to the SDRAM in SAMBA.
Is it possible that the 9263 got into some unrecoverable error state when it was powered up once with a bad power sequence? I’ve tried removing VDDBU power after startup, per the FAQ article on the Atmel website, but that didn't help.
Any help is greatly appreciated.

We had a lot of problems with BGA attachment of the processor chip initially, and this was one of the symptoms. If you have the capability, you may want to try and reflow or replace the processor.

I will try reflowing the chip. I had our CM X-ray the boards, and they found no issues, but it's worth a try.

I am experiencing some wierd issues with the external SDRAM as well. And I also have a power sequencing issue. I'll talk about that one first...
The order of the power up should be VDDCORE -> VDDIO -> VDDBU, according to Application Note 6249B. To me, this is a problematic sequencing order because VDDCORE and VDDBU are both 1.2V if you run the clock at 240MHz. The issue we're seeing is that VDDBU is tied in some way to VDDCORE, and thus the sequencing is all f'd up because VDDIOM is powering up too late. We measured about 88kOhms of resistance between VDDCORE and VDDBU, which is not nearly enough to provide isolation sufficient to sequence those two supplies independently.

I am not able to reliably write to SDRAM on these prototypes either. Like the OP, I had also done a previous prototype with nearly the exact same SDRAM configuration, and it worked fine but had no power sequencing. I have been wondering the same thing about the power up sequence, and I have contacted my local FAE, who has yet to respond to me about this issue. I will post as soon as I learn more.

It definitely makes me feel better that other people are experiencing this same problem.

Thanks for the suggestion, falingtrea. My SDRAM problem did turn out to be poor soldering on the BGA. The pins near A1 were receiving improper heat, and not all of them were making contact. This happens to be the corner where all SDRAM control signals come from. I was able to fix a handful of boards by reheating the chip. I hate lead-free BGAs.
For my power sequencing, I added a P-ch MOSFET in the power path for +3.3V, with the gate driven by the collector of a self-biased BJT and pulled through a 10k resistor to the source. The base of the BJT is driven by VDDCORE, which comes up quickly, and the emitter is tied to ground. This has worked well.
I found no issues related to VDDBU sequencing.

That is weird. Does that mean you can't battery backup the AT91SAM9263? Or is that the power up sequence if you don't have a battery backup?

falingtrea, the application note is in distinctly different sections for battery backup and no battery backup. Unfortunately, I cannot find the application note online a second time, which makes me wonder if it's been removed from the site.

At any rate, the Atmel factory response:
"Your customer is right, you will have energy on VDDBU if you powered VDDCORE first (due to the power switch). But this is not a problem at all as the device is under reset state.
Your customer can even reduce the bom, as VBBU could be powered at the same time as VDDCORE if VDDIO is established within Tres + Startup + T2 (1.2s) after VDDBU reached Vth+.
If he keeps the comparator or if he removes it (following the above condition), everything will boot correctly... The power up problem is related only to NVM boot."
I.e. the power sequencing described in the Atmel Application Note 6249B does not apply to the 9263.

To follow up, I removed all forms of power sequencing, and am still experiencing the same problem with the SDRAM. I have sent a few of my protoboards off to be x-rayed and reflowed, however I am not optimistic. It could be that the automation process was done incorrectly or the oven was not hot enough, however, after further testing I have seen that all of my boards exhibit this SDRAM problem, not just a few, which leads me to believe that there may be a problem with my layout, rather than the manufacturing process.
I will post again when the reflowed boards are returned to me and I have a chance to test them.

StaticAge,

Seeing similar problems on a G20 board. Our previous 9260 based boards with same design worked fine. This is the first BGA though.
Did re-flowing your chip solve your problem or was it power up timing after all ?

Thanks

Gertjan