Hi, i'm working with AT91SAM9XE and i am going to run my coded from its internal flash. Now i have two qeustion as follow:
1- what is maximum ARM MIPS when the code is run from internal flash?
2- Is there any one who can init MMU when the code is run from internal flash?

Best regards.

I started my project a year and a half ago with the 9XE and Atmel could not deliver so I respun my PCB with the 9G20. I am using FreeRTOS. I had the mmu running (init from flash) The big problem was the page tables wants to be in 16K and this ram space could not be shared with anything else, so you only have one 16K internal ram available. As I recall the flash could only run at 1/4 my CPU clock so you could guess 1/4 the rated MIPS (without cache). If you need more ram so that you are forced to use external, consider the 9G20, all you need is an SPI flash to boot it to external ram. If internal ram is enough you can place critical code in ram for full speed.

Hi DJFarrell

Could you share your initialization code for MMU init in flash ( AT91SAM9XE512 )?
I am facing some troubles to initialize the MMU in my AT91SAM9XE-EK. When MMU is enabled, the processor freezes. Probably I am coding wrong the Translation Tables. I need the MMU due Dcache enable.

Thanks.

hello,
maybe it's a little bit too late but better now then never.
Here is my code to initialize the mmu of the at91sam9xe to be able to use the d-cache.
It's mainly based on the atmel example "basic-dhrystone-project" but extended by also chaching the SDRAM:

//------------------------------------------------------------------------------
/// MMU Initialization
/// \param pTranslationTable Translation table adresse
//------------------------------------------------------------------------------
static void InitMMU(unsigned int *pTranslationTable)
{
int i;
int addSRAM;
int addSDRAM;

// Program the TTB
TRACE_DEBUG("TTB = 0x%X\n\r", (unsigned int)pTranslationTable);

CP15_WriteTTB((unsigned int)pTranslationTable);

// Program the domain access register
CP15_WriteDomainAccessControl(0xC0000000); // domain 15: access are not checked

// Reset table entries
for (i = 0; i < 4096; i++) {
pTranslationTable[i] = 0;
}
// Program level 1 page table entry
// Vector adress
pTranslationTable[0x0] = (0x00000000)| // Physical Address
( 1 << 10)| // Access in supervisor mode
(15 << 5)| // Domain
( 1 << 4)|
( 0 << 3)| // No D cache
0x2; // Set as 1 Mbyte section
// SRAM adress (with D cache)
addSRAM = (SRAM_ADDRESS >> 20);
TRACE_DEBUG("addSRAM = 0x%X\n\r", addSRAM);
TRACE_DEBUG("SRAM_ADDRESS = 0x%X\n\r", SRAM_ADDRESS);
ASSERT( addSRAM < 0xFFF, "PRobleme SRAM");
pTranslationTable[addSRAM] = (SRAM_ADDRESS)| // Physical Address
( 1 << 10)| // Access in supervisor mode
(15 << 5)| // Domain
( 1 << 4)|
( 1 << 3)| // D cache
0x2; // Set as 1 Mbyte section

for (i = 0; i <= 0x1F; i++)
{
// SDRAM adress (with D cache)
addSDRAM = (AT91C_EBI_SDRAM + (i * 0x00100000) >> 20);
pTranslationTable[addSDRAM] = (AT91C_EBI_SDRAM + (i * 0x00100000))| // Physical Address
( 1 << 10)| // Access in supervisor mode
(15 << 5)| // Domain
( 1 << 4)|
( 1 << 3)| // D cache
0x2; // Set as 1 Mbyte section
}

// Peripherals adress
pTranslationTable[0xFFF] = (0xFFF00000)| // Physical Address
( 1 << 10)| // Access in supervisor mode
(15 << 5)| // Domain
( 1 << 4)|
( 0 << 3)| // No D cache
0x2; // Set as 1 Mbyte section
}

regards
gerhard