Hi,
I'm designing a board using the AT91SAM9M10 with two banks of LPDDR, EBI1 also drives a 16 bit NAND.

1. Has anyone successfully used this configuration?
2. Do I use SDA10 on EBI1?
3. Is EBI0 ddr Vref required?
4. What's the reccomended termination scheme on the two buses?

many thanks for any responses

I am using an LP DDR with the AT91SAM9G45 and have been having problems. Watch out for clock speeds. As you can see from the datasheet, it appears that we cannot run full 133 MHz speed. Also, I put the DDR Vref on my board then removed it without issue. It appears that the DDR Vref is unused with LPDDR.

46.14 DDRSDRC Timings

The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR
modules. DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.

Supported speed grade limitations:
• DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
• LP-DDR (1.8V, 30pF on data/control, 10pF on CK)
Tcyc = 5.0 ns, Fmax = 125 MHz
Tcyc = 6.0 ns, Fmax = 110 MHz
Tcyc = 7.5 ns, Fmax = 95 MHz
• SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
• SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
• LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)

By the Way, My LPDDR is on the dedicated DDR bus and requires no termination scheme. My NAND is sitting all alone on the EBI bus on CS3 and requires no termination scheme. I am debating on the next revision to go back to DDR2 so I can run full speed again.

I am now running my board at 380 MHz with 95 MHz DDR clock / Sys Clock so that I can populate 7.5nsec DDR as well as 6 nsec and 5nsec DDR parts. If this holds stable under Linux 2.6.36 (has been running Qt all weekend taking screen captures to the RAM disk "/tmp" folde), I am going to move on...