SDRAM Initialization according to AT91SAM9260 datasheet says:

8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
devices, in particular CAS latency and burst length. The application must set Mode to 3
in the Mode Register and perform a write access to the SDRAM. The write address
must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.

So there are some questions that I can't understand!
1. There is no register to configue the burst length, is this done automatically by SDRAMC ?
2. I know the SDRAM device can get the Mode set value by the Mode Register Set Command, and the set value is just the address code.
But according above, the write access is arbitrary as long as BA[1:0] are set to 0. So, how can the SDRAM device get the mode set value ?

Thanks for help !!!!

oh! i have the same question. Please help.

for MT48L SDRAM that in bootstrap source file to init CAS latency to 2

write_sdramc(SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
writel(0xcafedede, AT91C_SDRAM+0x24); // Perform LMR burst=1, lat=2

the address performed is 0x20000024. but i can't understand because A4~A6 = 0x00 = Reserved...

CPU SDRAM Value (0x2000 0024)
A0 0
A1 0
A2 -- A0 1
A3 -- A1 0
A4 -- A2 0
A5 -- A3 1
A6 -- A4 0
A7 -- A5 0
A8 -- A6 0