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 Post subject: External SRAM memory
PostPosted: Fri Apr 01, 2011 1:00 am 
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Joined: Fri Apr 01, 2011 12:27 am
Posts: 3
Hello,

I have a doubt, I've built a custom board with an AT91SAM9G45. I placed in there an external SRAM memory, it is connected to the processor by the pins EBI1_D0 - EBI1_D15.

I'd like to know what more I have to do in order to allow the use of the SRAM memory.

I've found some interesting points in the bootstrap code, but there is only about ddram (ddram_init). I read in the processor document that I have to set the EBICS1A if I want to use the static memory controller, but I am not sure where to set that.


Thanks in advanced for any hint.


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 Post subject: Re: External SRAM memory
PostPosted: Fri Apr 01, 2011 1:37 am 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
You don't mention a part, timing, complete wiring, but you'd set it up like a 16-bit NAND device in the SMC (Static Memory Controller), with appropriate timings, etc.

Something along the following lines :

// Configure EBI
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SM;

// Configure SMC
AT91C_BASE_SMC->SMC_SETUP1 = 0x00000000;
AT91C_BASE_SMC->SMC_PULSE1 = 0x00030003;
AT91C_BASE_SMC->SMC_CYCLE1 = 0x00050005;
AT91C_BASE_SMC->SMC_CTRL1 = 0x00002003;

AT91C_BASE_SMC->SMC_CTRL1 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;

This would park it in the 256MB window at 0x20000000


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 Post subject: Re: External SRAM memory
PostPosted: Tue Apr 05, 2011 12:30 am 
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Joined: Fri Apr 01, 2011 12:27 am
Posts: 3
[quote="CptTitanic"]You don't mention a part, timing, complete wiring, but you'd set it up like a 16-bit NAND device in the SMC (Static Memory Controller), with appropriate timings, etc.

Something along the following lines :

// Configure EBI
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SM;

// Configure SMC
AT91C_BASE_SMC->SMC_SETUP1 = 0x00000000;
AT91C_BASE_SMC->SMC_PULSE1 = 0x00030003;
AT91C_BASE_SMC->SMC_CYCLE1 = 0x00050005;
AT91C_BASE_SMC->SMC_CTRL1 = 0x00002003;

AT91C_BASE_SMC->SMC_CTRL1 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;

This would park it in the 256MB window at 0x20000000[/quote]

Thank you very much for your reply! Now I am configuring the external SRAM as follows:

writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SMC, AT91C_BASE_CCFG + CCFG_EBICSA);
writel((0x00000000), AT91C_BASE_SMC + SMC_SETUP1);
writel((0x00030003), AT91C_BASE_SMC + SMC_PULSE1);
writel((0x00050005), AT91C_BASE_SMC + SMC_CYCLE1);
writel((0x00002003), AT91C_BASE_SMC + SMC_CTRL1);

I did not find a way to use as you told me like 'AT91C_BASE_SMC->SMC_SETUP1', but I think that this way is right, isn't it?

These values are what you said, because I don't know how to generate these values. The external SRAM that I do have here is 'CY62147EV30LL'. By its datasheet, its speed is 45ns. What more I have to know about the memory in order to have it ready to use?
And how I generate these numbers that you have mentioned?

Thanks in advanced.


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 Post subject: Re: External SRAM memory
PostPosted: Tue Apr 05, 2011 12:57 am 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
You'll have to translate the timing characteristics expressed on Pg 6, to the MCLK timing units (100 MHz = 10ns, 133 MHz = 7.5 ns) described in the G45 technical reference manual.

http://www.cypress.com/?mpn=CY62147EV30LL-45BVXI
http://www.cypress.com/?docID=26154


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 Post subject: Re: External SRAM memory
PostPosted: Wed Apr 06, 2011 12:38 am 
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Joined: Fri Apr 01, 2011 12:27 am
Posts: 3
[quote="CptTitanic"]You'll have to translate the timing characteristics expressed on Pg 6, to the MCLK timing units (100 MHz = 10ns, 133 MHz = 7.5 ns) described in the G45 technical reference manual.

http://www.cypress.com/?mpn=CY62147EV30LL-45BVXI
http://www.cypress.com/?docID=26154
[/quote]


Thank you again for your reply.

So the value that I insert by the command 'writel' is the number of 'timing units', right?

For example, in my case, the read cycle time is 45ns and the processor is running at 133 Mhz then it needs 6 cycles of clock (and in the case of this memory, the same to the write cycle).

Therefore, since the SMC_CYCLE register is organized like:

[31-25] [24-16:NRD_CYCLE] [15-9] [8-0:NWE_CYCLE]

Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles

Then I have a SMC_CYCLE '0x00060006' and so I must code something like:

writel((0x00060006), AT91C_BASE_SMC + SMC_CYCLE0);

I have not tried it yet because I did not find some other timings in the datasheet of the memory, for example I don't have the setup time of address before the NCS falling edge.

Anyway, is the way that I am coding and calculating the timing right?


Thank you!


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