[quote="CptTitanic"]You'll have to translate the timing characteristics expressed on Pg 6, to the MCLK timing units (100 MHz = 10ns, 133 MHz = 7.5 ns) described in the G45 technical reference manual.
http://www.cypress.com/?mpn=CY62147EV30LL-45BVXIhttp://www.cypress.com/?docID=26154[/quote]
Thank you again for your reply.
So the value that I insert by the command 'writel' is the number of 'timing units', right?
For example, in my case, the read cycle time is 45ns and the processor is running at 133 Mhz then it needs 6 cycles of clock (and in the case of this memory, the same to the write cycle).
Therefore, since the SMC_CYCLE register is organized like:
[31-25] [24-16:NRD_CYCLE] [15-9] [8-0:NWE_CYCLE]
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
Then I have a SMC_CYCLE '0x00060006' and so I must code something like:
writel((0x00060006), AT91C_BASE_SMC + SMC_CYCLE0);
I have not tried it yet because I did not find some other timings in the datasheet of the memory, for example I don't have the setup time of address before the NCS falling edge.
Anyway, is the way that I am coding and calculating the timing right?
Thank you!