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 Post subject: AT91SAM9R64 - PWMC interrupts are prioritized???
PostPosted: Wed Apr 06, 2011 12:03 am 
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Joined: Thu Oct 01, 2009 5:59 pm
Posts: 4
I am having some really strange behaviour in my PWMC interrupt. I have two different channels that are running on timebases that are a multiple of each other. As a result, sometimes when the interrupt occurs, multiple channels will need to be serviced. Here's the thing... when I read the ISR register three times in a row, I get different results each time!

If I put a breakpoint on the trchalt() call below, i=6, j=2, and a subsequent read of the ISR gives 0. Does this mean that I am supposed to get one interrupt for each channel, and only service the interrupt for that channel on that pass through???

static void PWMC_handler(void) {
volatile int i, j;

/* Clear ISR by reading it */
i = AT91C_BASE_PWMC->PWMC_ISR;

/* Check for anomalies. */
/* ISR should not still be set immediately after read. */
if ((j = AT91C_BASE_PWMC->PWMC_ISR)) {
trchalt();
}


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 Post subject: Re: AT91SAM9R64 - PWMC interrupts are prioritized???
PostPosted: Wed Apr 06, 2011 12:21 am 
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Joined: Thu Oct 01, 2009 5:59 pm
Posts: 4
Wait... it gets weirder. How can I have an interrupt for both channels 1 and 2 (0x6) when only interrupts for channel 2 are enabled (0x04)? The last two words below are the (read only) PWM_IMR and PWM_ISR registers.

(gdb) x/8wx 0xfffc8000
0xfffc8000: 0x00000507 0x00000000 0x00000000 0x00000006
0xfffc8010: 0x00000000 0x00000000 0x00000004 0x00000006

Greg


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