I've recently designed a prototype PCB with the AT91SAM9RL processor (http://www.atmel.com/dyn/resources/prod ... oc6289.pdf). The SDRAM memory is wired up in a similar manner to the evaluation kit schematic (http://www.atmel.com/dyn/resources/prod ... oc6325.pdf). On page 29 of this document, two SDRAM chips are shown.

On my custom circuit board, I am using two SDRAM chips of the MT48LC16M16A2BG-75:D TR from Micron (http://download.micron.com/pdf/datashee ... MSDRAM.pdf).

As shown in the evaluation kit schematic, both SDRAM chips share the same address bus. However, one SDRAM chip is wired to D[0:15] of the data bus, whereas the other is wired to D[16:31] of the data bus.

On my prototype PCB, the first SDRAM chip (wired to D[0:15]) does not work very well due to connection problems on the PCB. It appears that the pads underneath of this chip are badly damaged.

Is there a way to set up the SDRAM controller on the AT91SAM9RL processor to only use the second SDRAM chip (wired to D[16:31])?

I could then safely remove the first SDRAM chip, and only use the second SDRAM chip (wired to D[16:31])). If this is possible, what would I have to change in AT91bootstrap (or U-Boot) to be able to do this? I intend to eventually run Linux on this embedded system, but I strongly believe that the SDRAM setup is done in AT91bootstrap.

I would be extremely indebted if anyone knows anything that I could do in this situation.

You are correct that this gets set up in AT91Bootstrap, however I am not aware of any method to swap the high/low 16-bit data bus.

Thanks for your response, CptTitanic; this is greatly appreciated!

The idea of swapping the 16 bits of the data bus is quite tantalizing to me, since it appears that there are two jumper resistors (R29 and R30) on the SDRAM chip select signal, as shown on page 29 of the evaluation kit schematics (http://www.atmel.com/dyn/resources/prod ... oc6325.pdf).

Removing one of these resistors would effectively disable the first (or second) SDRAM chip. Note that either the first or the second SDRAM chip can be disabled. I don't know if this was simply a debugging feature during hardware development, or if this points to the possibility of using either the first or the second SDRAM chip.

Sometimes I feel like an archaeologist trying to find how the Great Pyramid was built!

Perhaps this would be done by the addressing? The {A0, CFIOR-NBS1-NWR1} and {A1, CFIOR-NBS3-NWR3} signals would have to be swapped, but then this also creates the issue of swapping the D[16:31] signals as well.