Hello,

The sam9g45 I am using has a 32MB DDR2 chip. Some of my code executes out of this DDR memory, and there are at least 3 DMA transfers that access the memory during normal program execution (ISI, UDPHS, and sometimes the LCD controller).

I'm noticing sometimes that my data is getting corrupted on the ISI DMA transfer. I'm somewhat new to this so I'm trying to figure out what possible problems could be. I was actually quite surprised that the memory controller couldn't arbitrate these simultaneously without any errors (I would understand if it slowed down). Then again I could be messing up my memory settings or something else in my code. Maybe I just have to set something up?

Also I was just playing around with some of the registers in the DDRSDRC and Noticed the HS register. Does anyone have more documentation on what this register is used for? The prelim seems incomplete.

I seem to have found one solution in the Bus MATRIX by changing the allowed burst length of the UDPHS Master from unlimited to <= 32 beats. It seems like you have a lot of control over the bus with this User Interface.

Anyone ever modify these values (or arbitration priorities) on their own projects? I would be interested to hear problems you did/didn't run in to.

Ben