The 9G45 timing specs for ethernet RMII mode are very loose. I don't know of any PHY chips that can be guaranteed to work with it. For example, the DM9161A on the eval board has a minimum setup time requirement of 4ns on ETXn or ETXEN toggling before the rising edge of the transmit clock. The 9G45 timing spec (EMAC21 on apr 2011 datasheet) allows for a state change 2.2ns before the clocking edge (20ns - 17.8ns). I asked Atmel support about this and they say that they do not have an errata for this, and to please respect the datasheet values.

The eval board is in violation of this spec. At least two other chips, one from Micrel and one from National) have an identical spec to the DM9161, so they would also not be usable in RMII mode.

I suggest designing using the MII connection, where any of these same PHYs would be guaranteed to have timing margin.

G. Pontis