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 Post subject: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Fri Aug 26, 2011 6:44 pm 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
Hello,

I am wondering if it is possible to wire up two 512 Mbit SDRAM chips (Micron MT48LC32M16A2P-75 IT:C TR, with datasheet: http://download.micron.com/pdf/datashee ... bSDRAM.pdf) to the EBI of the AT91SAM9G20B processor (http://www.atmel.com/dyn/resources/prod ... oc6384.pdf).

Each chip is 32M x 16.

The two chips would connected in the same fashion as the SDRAM chips on the evaluation kit circuit board (see page 31): http://www.atmel.com/dyn/resources/prod ... oc6413.pdf

I know that I would have to change the AT91bootstrap source code to use these chips, but I am wondering if 128 Mbytes of memory is supported by the AT91SAM9G20B processor. Could anyone comment on this?


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Fri Aug 26, 2011 8:04 pm 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
I'm using one MT48LC32M16 on a G20, I'd just have to double the bus width from 16 to 32-bit to use two of them.

You're constrained by the 256 MByte window, and the row, column, bank, width as defined in the manual.


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Fri Aug 26, 2011 8:33 pm 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
Great to hear; thank you for confirming this, CptTitanic. This is much appreciated! I will use the MT48LC32M16 with a 32-bit bus width by updating the AT91bootstrap code.

Once again, thank you!


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Sun Oct 23, 2011 6:21 pm 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
Now that I've finally designed and built the hardware for an AT91SAM9G20 board, I would like to modify AT91bootstrap and SAM-BA to use two 512 Mbit SDRAM chips. Looking at the datasheet for the Micron MT48LC32M16A2P-75 IT:C TR (http://download.micron.com/pdf/datashee ... bSDRAM.pdf), it appears that the only required change to the SDRAM setup code is the number of column bits.

My custom PCB has SDRAM wired up in the same way as the evaluation kit. Two SDRAM chips are being used. Here is what I have modified in AT91bootstrap:

sdram_init( AT91C_SDRAMC_NC_10 | // Column bits (changed from AT91C_SDRAMC_NC_9)
AT91C_SDRAMC_NR_13 |
AT91C_SDRAMC_CAS_3 |
AT91C_SDRAMC_NB_4_BANKS |
AT91C_SDRAMC_DBW_32_BITS |
AT91C_SDRAMC_TWR_3 |
AT91C_SDRAMC_TRC_9 |
AT91C_SDRAMC_TRP_3 |
AT91C_SDRAMC_TRCD_3 |
AT91C_SDRAMC_TRAS_6 |
AT91C_SDRAMC_TXSR_10,
(MASTER_CLOCK * 7)/1000000,
AT91C_SDRAMC_MD_SDRAM);


However, this change does not seem to work, and programs loaded into SDRAM do not run. I've also written some code to read and write test patterns into SDRAM, and the reads do not compare to the written patterns.

Perhaps something else needs to be changed related to SDRAM signal timing?

It appears that another thread on this forum touched on a similar issue for another processor (viewtopic.php/f,9/t,3506/). I believe that the same memory chip is being used. The solution given in this older thread was to switch the SDRAM manufacturer (Samsung instead of Micron), but I don't think this is necessary.


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Mon Oct 24, 2011 5:17 pm 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
I'm using exactly those settings, except the AT91_SDRAMC_DBW_16_BITS. You could use the 16-bit width also, it would just used one device.

Using an MT48H32M16LFBF-75 IT:B, running the memory at 133 MHz, 1.8V, and not committing the PC[16..31] pins to the upper data bus.

Is there any pattern to the bits that aren't working?
Is the data there if you read it back within a few cycles?
Does the value of MASTER_CLOCK reflect what speed it is set up for in the PLL's, the target is 7.81 us (ie 8192 accesses in 64 ms)?


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Tue Oct 25, 2011 3:02 am 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
Thank you very much for your response, CptTitanic; it is very much appreciated!

I've removed a zero ohm jumper resistor on my custom board to disconnect the chip select of the second SDRAM (connected to data bits D[32:16] on the EBI bus). After modifying SAM-BA and At91Bootstrap for a 16-bit SDRAM, I've found that the first SDRAM chip (connected to data bits D[15:0] on the EBI bus) works normally using the following call to sdram_init in At91bootstrap:

sdram_init( AT91C_SDRAMC_NC_10 | // Column bits
AT91C_SDRAMC_NR_13 |
AT91C_SDRAMC_CAS_3 |
AT91C_SDRAMC_NB_4_BANKS |
AT91C_SDRAMC_DBW_16_BITS |
AT91C_SDRAMC_TWR_3 |
AT91C_SDRAMC_TRC_9 |
AT91C_SDRAMC_TRP_3 |
AT91C_SDRAMC_TRCD_3 |
AT91C_SDRAMC_TRAS_6 |
AT91C_SDRAMC_TXSR_10,
(MASTER_CLOCK * 7)/1000000,
AT91C_SDRAMC_MD_SDRAM);


I've written standalone test programs to read and write data into the SDRAM chips, and I find that there is indeed a pattern to the bits that are not working.

When configured as a 16-bit bus for one SDRAM chip, reads and writes to SDRAM work normally up to (64*1024*1024) memory locations (64 MB). This is normal behavior.

However, when I set up the SDRAM using AT91C_SDRAMC_DBW_32_BITS, and when I use both of the SDRAM chips, I've found that reads to memory do not work for accessing locations greater than (64*1024*1024).

For memory locations greater than (64*1024*1024), the bits read from SDRAM are all high (0xFFFFFFFF).

I've added the following test code to AT91bootstrap. This test code is similar to my standalone program. When the counter variable exceeds (64*1024*1024), the bits read from SDRAM are all high.

#define MEM_START AT91C_EBI_SDRAM // AT91C_EBI_SDRAM address 0x20000000
#define MEM_SIZE 128*1024*1024
#define TEST_NUM 0xAAAAAAAA

void test_memory( void )
{
unsigned int *ptr = (unsigned int *) MEM_START;
int i;

dbg_print("Starting memory test and filling locations...\n\r");
for (i = 0; i < MEM_SIZE; i++)
ptr[i] = TEST_NUM;

dbg_print("Reading back test data...\n\r");
for (i = 0; i < MEM_SIZE; ++i) // fails for i greater than 64*1024*1024
{
if(ptr[i] != TEST_NUM)
{
dbg_print("Memory test did not pass\n\r");
return;
}
}
dbg_print("Memory test passed\n\r");

} // end of function



There is a section of the datasheet (Bus Matrix Master Remap Control Register, pg. 132) that may suggest bus remapping is required to use EBI memory locations greater than 64*1024*1024. Here is a link to the datasheet: http://www.atmel.com/dyn/resources/prod ... oc6384.pdf.

In my At91bootstrap code, I've turned on bus remapping:

writel( AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D, AT91C_BASE_MATRIX + MATRIX_MRCR );

However, bus remapping still causes the above code to fail.

Perhaps we are dealing with an obscure hardware bug? I've checked the SDRAM connections, and everything appears to be wired up correctly.


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Tue Oct 25, 2011 3:06 am 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
The MASTER_CLOCK and PLL settings are the same in the generic AT91bootstrap code provided by Atmel for the AT91SAM9G20 evaluation kit. I haven't changed any of the code written by Atmel:

#define MASTER_CLOCK (132096000)
#define PLL_LOCK_TIMEOUT 1000000

#define PLLA_SETTINGS 0x202A3F01
#define PLLB_SETTINGS 0x10193F05

/* Switch MCK on PLLA output PCK = PLLA/2 = 3 * MCK */
#define MCKR_SETTINGS 0x1300
#define MCKR_CSS_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS)


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Tue Oct 25, 2011 4:19 am 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
On the other hand, using the 32-bit configuration (with two 512 Mbit SDRAM chips and associated setup in At91bootstrap), I can now load U-boot from the external dataflash to SDRAM. The U-boot memory test (mtest) seems to work without any errors (after updating the U-boot code so that the test does not overwrite any critical sections). I can now read and write values into SDRAM. Writing 0x10 words (16 words) of 0xAAAAAAAA starting at memory location 0x24000001:

U-Boot> mw 0x24000001 0xAAAAAAAA 0x10
U-Boot> md 0x24000001 0x10
24000001: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................
24000011: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................
24000021: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................
24000031: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................

The mw command writes into memory, and the md command displays memory.

So maybe the test_memory( void ) function that I wrote isn't working, and the two SDRAM chips are indeed working as expected?

Doing a similar test a few minutes later shows that the 16 values are still in SDRAM memory, along with some garbage data (uninitialized memory locations?):

U-Boot> md 23FFFFFF 0x20
23ffffff: efefffff aaaaaaaa aaaaaaaa aaaaaaaa ................
2400000f: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................
2400001f: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................
2400002f: aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa ................
2400003f: aaaaaaaa ffffffff ffffffff ffffffff ................
2400004f: ffefffff ffffffff ffffffff ffbfffff ................
2400005f: fffeffff ffffffff ffffffff ffffffff ................
2400006f: ffefffff ffffffff fffffff7 ffffffff ................

I did not have to turn on bus remapping to get this result. All that I had to modify was the AT91C_SDRAMC_NC_10 and AT91C_SDRAMC_DBW_32_BITS defines, for SDRAM chips with 10 column bits and a 32-bit bus.


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Tue Oct 25, 2011 9:34 pm 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
Here's how I'm exercising the SDRAM

void TestSDRAM(void)
{
unsigned int hole = 0x10000; // SDRAM used by my app, zero if running from SRAM
unsigned int size = (64 * 1024 * 1024); // 64 MB
unsigned int i, j;
static unsigned int k = 0xFFFFFFFF; // Rolling Seed
unsigned long *p = (unsigned long *)(0x20000000 + hole); // Base of SDRAM

puts("Filling SDRAM");

// Memory Fill
j = k;
for(i=0; i<((size - hole) / sizeof(unsigned long)); i++)
{
p[i] = j;
if (j & 0x80000000)
j = (j << 1) ^ 0x04C11DB7; // Polynomial for a 32-bit CRC, reasonable LFSR
else
j = (j << 1);
}

// Insert delay here if desired, >64ms

puts("Checking SDRAM");

// Memory Check
j = k;
for(i=0; i<((size - hole) / sizeof(unsigned long)); i++)
{
if (p[i] != j)
{
printf("SDRAM fail @ %08X, read %08X, expect %08X\n",(unsigned int)&p[i],p[i],j);
break;
}
if (j & 0x80000000)
j = (j << 1) ^ 0x04C11DB7; // Polynomial for a 32-bit CRC
else
j = (j << 1);
}

if (i >= ((size - hole) / sizeof(unsigned long)))
puts("SDRAM pass");

k = j; // Update seed, so next pass uses different pattern
}


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Wed Oct 26, 2011 3:18 am 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
That's brilliant; thank you very much CptTitanic for posting the code that you've used to check SDRAM! I particularly like the use of the shift register to generate changing values for each memory location.

By running your code in internal SRAM (hole = 0) and changing the memory size to (128 * 1024 * 1024), I can verify that 128 MB of SDRAM on my custom board successfully passes your test.

I have one final question: Why is the memory size normalized by sizeof(unsigned long), which I assume is 4 bytes (32-bits) on an ARM processor?

What is the significance of the (size - hole) / sizeof(unsigned long) maximum array index used in the filling and comparison loops?


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Wed Oct 26, 2011 3:39 pm 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
I haven't checked this particular polynomial, but I suspect it is probably ((2 ^ (N-1)) - 1), ie maximal 31 bit, with two domains. I could probably find a 32 bit maximal one, but as you note it generates a changing stream that is easy to repeat, and is much more likely to catch address/data bus failures.

The sizeof() issue come from the fact that &p[0] = 0x20000000, and &p[1] = 0x20000004, consequently the index will be one quarter of the memory size in bytes. I use sizeof() instead of assuming 32-bit, as it is a more portable construct.


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 Post subject: Re: Using two 512 Mbit SDRAM chips with AT91SAM9G20B
PostPosted: Wed Oct 26, 2011 5:42 pm 
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Joined: Fri Oct 22, 2010 4:25 am
Posts: 43
Thanks, CptTitanic; this is greatly appreciated. I can now confirm that the two SDRAM chips pass the memory test. This solution works well for me.

Once again, thank you.


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