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 Post subject: SAM9XE peripheral initial state
PostPosted: Fri Oct 28, 2011 1:05 pm 
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Joined: Fri Oct 28, 2011 12:44 pm
Posts: 5
Hi All,

Device is SAM9XE (9260). I've got a question regarding controlling the initial state of IO line, if it's been assigned to a peripheral.

We are setting registers to drive PIO lines using the Atmel bootstrap. On reset, the lines in question reset to inputs. We want a particular line to be output and controlled by a peripheral (e.g. TD0 on SSC controller) . We are trying to control the initial state driven by a line which is set to be controlled by a peripheral. Can SODR/CODR be used for this?

The question is, does it mean that regardless of whether we will have PIO enabled or using peripheral on a line, can we control the actual initial logic level to be driven on the pad by setting the output and the set/clear registers, given that peripheral is selected for the pad in bootstrap.

If this is the case, then in timing terms, does this mean that the output status registers assert themselves on the pad prior to the output of the chosen peripheral, as it controls the initial state, even if peripheral is selected? Or are the output registers written before the PER/PDR registers?

However, if our reasoning is incorrect and the OSR and ODSR does not assert itself on the pad if PIO is disabled in bootstrap, how do we actually control the initial logic level driven by the line? E.g. set or disable pull-up resisters or some other way?

The datasheet (section 31.4) says:
1. Setting PIO_SODR and PIO_CODR affects PIO_ODSR, which defines the first level driven on the IO line.
2. The IO line can be configured by PIO_OSR and PIO_CODR prior to setting it to be managed by the PIO controller, regardless of whether the pin is configured to be controlled by PIO or assigned to a peripheral function.
3. When the I/0 line is assigned to a peripheral function, the drive of the I/O line is controlled by the peripheral.

Thanks for your help!
Richie


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 Post subject: Re: SAM9XE peripheral initial state
PostPosted: Fri Oct 28, 2011 1:46 pm 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
You should be able to control the state of the pin up to the time the peripheral takes control of it.

Generally it's bad form to expect pins to do anything during a reset, and you should be able to bring up external devices in a controlled manner. A standard power on reset can last hundreds of milliseconds, plus time to get PLLs to lock.

You should be able to measure how long it takes with a scope.

You should set up the critical PIOs before starting the PLL.

Pins that turn to inputs could safely be pulled up/down with a 100K. When turned to a push-pull driver this will easily be overcome.


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 Post subject: Re: SAM9XE peripheral initial state
PostPosted: Fri Oct 28, 2011 2:03 pm 
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Joined: Fri Oct 28, 2011 12:44 pm
Posts: 5
Thanks for your reply, very helpful.

I've seen elsewhere that all (32bits of) registers can be set in one go, or in a set/clear mode, which is staggered, but as far as I can see from the Atmel bootstrap API, all register configuration is set at the same time.

Therefore to control the line states with exernal devices attached, would I need to first set the lines as PIO/IO, insert a brief delay (to allow the the lines register to a state), then configure as Peripheral and set PLL? Or is it a function of the processor to always assert the values in the output status registers before the PLL and peripheral kicks in, even if output and peripheral/PLL registers are set at the same time?

Best way would of course be to see what comes up at a scope, but my scope time is booked for next week, so until then, I'd like to understand theoretically what should happen to write some code!


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 Post subject: Re: SAM9XE peripheral initial state
PostPosted: Fri Oct 28, 2011 4:01 pm 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 574
If you want speed you program the registers directly, not via an API.

You have control of the pins until they are assigned to a peripheral, after that the peripheral controls them.

The PLL issue is one of time spent in spin-loops.

If you want to address the pins quickly, you must put code in the reset routines to address them immediately. You can do this before setting up other more latent tasks.

Something like this

; Peripheral Clock Enable
LDR R0, =PMC_BASE
LDR R1, =0x00000010 ; PIOC
STR R1, [R0, #PMC_PCER_OFS]

LDR R0, =PIOC_BASE ; Set PC[16..31] Output/High
LDR R1, =0xFFFF0000
STR R1, [R0, #PIO_SODR_OFS] ; PIO Value Set
STR R1, [R0, #PIO_OER_OFS] ; PIO Output Enable
STR R1, [R0, #PIO_PER_OFS] ; PIO Controls (PIO not Peripheral)


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 Post subject: Re: SAM9XE peripheral initial state
PostPosted: Fri Oct 28, 2011 6:32 pm 
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Joined: Fri Oct 28, 2011 12:44 pm
Posts: 5
Thanks, I now understand what needs to be done!


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