Hello everybody,

I have a problem with ADC - AT91SAM9G20. I use ADC with 10 bit resolution - ADC clock ís max 1MHz. When I set ADC_MR register, max value prescal is 63 and so ADC clock is 1 032 000Hz, but max value is 1MHz (MCK is 132MHz).

I used :
ADC_MR = ( (0x3F << 8) | (0x2 << 16) | (0x1 << 24) );
Prescal = 63 -> ADC clock =1 032 000 Hz
StartUP = 2 -> Startup time = 2,32e-5 s
SHTIM = 1 -> Sample and Hold Time = 1,93e-6 s

Can you help me, please?
Thank you

So if the clock is critical (ie can't handle +3% variation), then you'll need to tweak the CPU/MCLK so they are 3% slower. The PLLs are quite flexible in this regard.