Hello

DDR2SRC

Why does A0 from the cpu bus go to A0 on the DDR2 chips?
If this is the case, then how does it manage the odd / even bytes and addresses on the 16 bit bus?

Is A0 on the bus really A1 or what am I missing here???

I ask this because with the current situation, I am no able to calculate at what addresses the banks will switch.

Best regards
Bernt

Because Dynamic memories are addressed by latching ROW and then COLUMN addresses. These SHARE A[12..0]

The BANK is sent via BA[1:0]

Where the bank transition occurs depends on the bit width of the ROW and COLUMN programmed into the SDRAM/DDR Controller, and the bit width of the memory interface. Want to see how these bits stack up, search "Linear Mapping for SDRAM Configuration" in the product documentation.

Hello and thanks for the reply!

According to that section you mentioned, Table 22-3, the DDR_A0 line is in actual fact the processor A1 line.
I thought so but the app note on the DDR2 implementation clearly states that DDR_A0 goes to the bus A0. So this is incorrect and majorly confusing.

I now see the processor A0 line is conenctod to M0. I assume this is the DQM0 line to the DDR2?
For a 16 bit bus width. Where in the cpu is M1 (DQM1? connected then)?

Best regards

Bernt

It's accessing the memory via ROWs and COLUMNs, not as a linear address like the static memory model you're trying to apply here.

The bit width of the ROW [A12..A0] and COLUMN [A12..A0], is defined by the SDRAM/DDRs geometry which you have to program into the controller.

The ARM memory view A1..A0 for a 32-bit access never get to the external bus. The stuff on the external bus is first the ROW# which is latched, then the COLUMN#, subsequent memory accesses automatically increment inside the memory chip so a stream of data can be burst read from the device.

The wiring of the SDRAM doesn't change for 16 or 32-bit wide implementations, you just route the data bits to the correct devices, the address bits remain the same, the controller handles the address sequencing, and the synchronous/sequential access properties. You can in fact run a board with a 32-bit memory subsystem in 16-bit mode, you just halve your memory and stop using half the chips. In a board with two chips, you could have a BOM that omitted the second chip for a lower cost/performance system, using the same board.

Hello and thanks again!

I understand what you you wrote but I still don't understand the exact operation of the Low byte / high byte operation for the standard 2 chip (D0-D7) (D8-D15) implementation.

Both chips see the same address lines, the same RAS/CAS and the same CS.
So how does it read from odd addresses? ie 0x201,203 etc?
Even if it can only do 16 bit reads / writes then the address still has to increase in steps of 2 so A0 from the cpu still cannot be used.

It has to have A1 from the cpu conencted to A0 on the RAM and it then also has to have 2 Low /High byte control lines ?


Best regards
Bernt

The DQSx and DQMx lines control specific bytes, and memories.

Odd reads are handled by the processor, and bus controller, to shift or cherry pick bytes from the data bus.

The ARM9 does not permit unaligned 32-bit reads.

Got it! Thank you very much!