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 Post subject: sam9g45 2nd SPI not working, no chip select signal
PostPosted: Wed Apr 11, 2012 11:27 pm 
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Joined: Tue Oct 18, 2011 9:10 pm
Posts: 7
Hi everyone, we have a customer board based on the sam9m10g45 EK, we use both SPI ports.

Now the 1st SPI works fine.

The 2nd is not. We saw clock, MOSI in the scope, but chip select was never on.

The only difference between the 2 SPIs are the clk/cs/miso/mosi pin settings. I dumped the control reg, mode reg, status reg, chip select register 1 (which we're using). The values are the same for both SPI.

Any suggestions ?


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 Post subject: Re: sam9g45 2nd SPI not working, no chip select signal
PostPosted: Thu Apr 12, 2012 1:06 am 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 784
Things are always a lot easier to troubleshoot when details of the OS, and pin/peripheral configuration code is provided for review.

Configuring things is half the battle, the other is to watch for external pin conflicts.


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 Post subject: Re: sam9g45 2nd SPI not working, no chip select signal
PostPosted: Thu Apr 12, 2012 2:11 am 
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Joined: Thu Apr 12, 2012 2:00 am
Posts: 1
Try to understand what's in the sources found on Micromint's website.

I suspect you didn't set the LASTXFER bit correctly.

Cheers!

@ admin:
what's with the SQL injection warning?


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 Post subject: Re: sam9g45 2nd SPI not working, no chip select signal
PostPosted: Thu Apr 12, 2012 4:05 am 
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Joined: Sat Oct 30, 2010 6:04 pm
Posts: 784
razvans wrote:
what's with the SQL injection warning?


The site is on a hair trigger, certain words set if off, the SQL one on words like s-e-l-e-c-t-i-o-n

There is also another pit of censored if you access the site from different IP addresses or devices (think mobile), when it will lock you out for extended periods.


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 Post subject: Re: sam9g45 2nd SPI not working, no chip select signal
PostPosted: Sat Apr 14, 2012 3:55 am 
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Joined: Tue Oct 18, 2011 9:10 pm
Posts: 7
i've simplified code like this,
other than the clk, miso, mosi, chip select pins,
all other config are the same.

so if i just build kernel with spidev0.0, it works.
if the kernel just has spidev1.0, the chip select signal always stay active low.

Here spidev1.0 means the slave 0 of the 2nd SPI,


CptTitanic wrote:
Things are always a lot easier to troubleshoot when details of the OS, and pin/peripheral configuration code is provided for review.

Configuring things is half the battle, the other is to watch for external pin conflicts.


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