Generate Clock at PCK0.

malkowki · **Joined:** Wed Jun 20, 2012 4:17 pm **Posts:** 2

Hello,

We are running Kernel 3.3.1 on the Olimex board SAM9-L9260 with AT91SAM9260 and we wanted to generate 20MHz or Higher clock rate on PCK0.
for this we activate at start up the PLLB and in the module we get and enable the pkc0 suing the following code:
get_clk(pck0)
clk_enable(pck0)
then
at 91_set_A_periph(AT91_PIN_PB30,1).
The clock signal quality is poor and getting worse when higher in frequency.see pictures.
Is there any maner to generated a clean signal?
Thanks in advance for your support.

CptTitanic · **Joined:** Sat Oct 30, 2010 6:04 pm **Posts:** 784

What kind of load do you have it driving into? Have you tried using a buffer.

malkowki · **Joined:** Wed Jun 20, 2012 4:17 pm **Posts:** 2

Hi,

I am not loading yet the PCK0(PB30) pin, since it should generate a clock signal I am just monitoring it using very low capacitive scope probe(9pF).
such a small load couldn't influence the signal quality?
I am just wondering why the signal from this ATMEL91 PLL is soo poor when going higher in frequency?

Generate Clock at PCK0.

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