My PCB hardware design uses one AT91SAM9G20 and two 133M SDRAM. Now I'm using Cadence Allegro, PCB SI to timing simulate the signals between 9G20 and SDRAM. But I can't find 9G20's SDRAM Controller's Timing Parameters in 9G20's Data Sheet. The Timing Parameters includes such as:
1. SDCKE High before SDCK Rising Edge;
SDCKE Low after SDCK Rising Edge;

2.SDCKE/SDCS/RAS/CAS/SDWE Low before SDCK Rising Edge;
SDCKE/SDCS/RAS/CAS/SDWE Hign after SDCK Rising Edge;

3. SDA10/BANK/DQM Change before SDCK Rising Edge;
SDA10/BANK/DQM Change after SDCK Rising Edge;

4. Address Change before SDCk Rising Edge;
Address Change after SDCK Rising Edge;

5. D0-D31 in Setup before SDCK Rising Edge;
D0-D31 in Hold after SDCK Rising Edge;

6. D0-D31 Out Valid before SDCK Rising Edge;
D0-D31 Out Valid after SDCK Rising Edge;

But the above all parameters can be found in AT91SAM9260 and AT91SAM9261's Data Sheet. But these two MCU can only support SDRAM which speed is below 100M.

Where can I get these parameters for AT91SAM9G20?

Thanks.

Here is the SDRAM Controller's timing parameters of 9260 (<100M).



What I want is just these parameters of 9G20 (133M).