Hello ,

im using the atmel AT91RM9200 basic boot sequence provided on the atmel site, in the cstartup_ram_ads.s file which is part of the AT91RM9200-BasicBoot-ARM1_2-2_0 package. The PMC configuration portion of the assembly code has raised some doubts.

In the following code,

1. what is the logic behijd selecting a "dirty CSS" value?what is the dirty CSS value and how dyu select it?
2. the dirty CSS value selected correspons to selecting PLLB as the clock source but PLLB is never configured so wont it create a situation where there is no clock ? ( coz PLLB output is 0 when DIVB is 0 on reset?)

3. And in the next few instructions, the CSS and PRES fields are written together, ignoring the guidelines given for configuring the MCKR register given in the errata for this product:

;------------------------------------------------------------------------------
;Step 0a.
;------------------------------------------------------------------------------
;-After reset, Slow Clock is normally selected
;-But in case of a boot already started, re-selection of Slow Clock
;-In two steps because of constraints of the Master Clock selection sequence
;-Can be cleared if the project is used for a boot execution
;------------------------------------------------------------------------------
ldr r1, = AT91C_BASE_PMC ; Get the PMC Base Address

;------------------------------------------------------------------------------
;-Write in the MCKR dirty value concerning the clock selection CSS then overwrite it in a second sequence
;------------------------------------------------------------------------------
;-Master Clock Register PMC_MCKR : "dirty CSS" is selected
ldr r0, = AT91C_PMC_CSS_PLLB_CLK
str r0, [r1, #PMC_MCKR]

;- Reading the PMC Status register to detect when the Master Clock is commuted
mov r4, #0x8
MCKR_Loop
ldr r3, [r1, #PMC_SR]
and r3, r4, r3
cmp r3, #0x8
bne MCKR_Loop

;------------------------------------------------------------------------------
;-Second sequence
;------------------------------------------------------------------------------
;-Master Clock Register PMC_MCKR : Slow Clock is selected
ldr r0, = AT91C_PMC_CSS_SLOW_CLK :OR:AT91C_PMC_PRES_CLK
str r0, [r1, #PMC_MCKR]

;- Reading the PMC Status register to detect when the Master Clock is commuted
mov r4, #0x8
MCKR_Loop2
ldr r3, [r1, #PMC_SR]
and r3, r4, r3
cmp r3, #0x8
bne MCKR_Loop2



thanks

Mayank

Hi,

1. what is the logic behijd selecting a "dirty CSS" value?what is the dirty CSS value and how dyu select it?

=> this "dirty CSS" value refers to the CSS value you have after your previous initializations. I remember that Step 0a concerns only the cases where some previous init on the PMC were done. If you boot just after reset on this code, all the step 0a must be deleted as explained in the source code.

2. the dirty CSS value selected corresponds to selecting PLLB as the clock source but PLLB is never configured so wont it create a situation where there is no clock ? ( coz PLLB output is 0 when DIVB is 0 on reset?)

=> PLLB is selected because all this step (step 0a) must be considered if some previous intitilaizations of the PMC were done, and in this case, this supposes that a previous initialization of the PLLB has been made.

3. And in the next few instructions, the CSS and PRES fields are written together, ignoring the guidelines given for configuring the MCKR register given in the errata for this product:

=> NO:
Initial case: CSS=PLLB and PRES!=0
first select CSS=PLLB and PRES=0 ( PRES is changed )
then CSS=SCLK and PRES=0 ( CSS is changed )

Bye !