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I has 16 data lines (DB0..DB15) which is for the bus interface. /CS , RS , /WR , /RD are for the SPI interface which I don't want to use.
I'm sorry, but that isn't true.
/CS, RS (which is effectively an address line for selecting between 2 memory-mapped registers), /WR, and /RD are all for the BUS interface.
SPI is formed by SDI, SDO, and an override of /WR which is referred to by the spec as SCL (the SPI clock) as well as as double-use of /CS.
PIO controller?
My apologies - I don't mean to be rude - but is your background primarily PIC, AVR, etc.?
Folks from those background tend to do have no experience with a bus and assume that it means "PIO", especially due to similar naming conventions between some teeny microcontrollers and things like 'D0, D1, D15, ...'. The data bus isn't to be connected to a "PIO port". (At least not in any efficient manner.)
In short - and this isn't something you should design around, you should find some references first; at the very least, read the SMC section of the 9260 users manual.
ILI /RD goes to the 9260 /RD (which doubles as /OE)
ILI /WR goes to the 9260 /WE
ILI /CS goes to any of the 9260 /CS# lines - choose one that doesn't conflict with other features multiplexed on pins that you're using (SDRAM, Ethernet, SPI, whatever.)
ILI D[17:0] go to the 9260 D[17:0], although I'd recommend putting a transceiver on that bus right next to the 9260, tristated if /CS# isn't low and direction determined by /RD and /WR. If you don't, you can quickly generate noise on a bus that's shared and runs very fast for the SDRAM.
ILI RS really ought to go to A2; align the 2 ILI registers on 32 bit boundaries.
Then read the SMC section labelled 'Coding Timing Parameters'. The particular chip select needs to be set up with timing values that fit the ILI part (it's an asynchronous part with listed timing; i.e., after a read attempt, it will place data on the data bus in x nanoseconds, and it will cease asserting the bus y nanoseconds after /CS goes high, etc.)
I'm sorry if this sounds more complex than you'd hoped for.
