Hello,

I'm thinking about to start a new project using a SAM3U device. I have a question about the SAM3U DMA controller. I did not get the answer out of the data sheet .

Is it possible to access an external RAM via DMA? I would like to use external RAM<->RAM respectively external RAM<->memmapped IO accesses by the DMA controller.

Thank you very much.

Hi,

Yes you can do it with the SAM3U. You can see an example with the demo on SAM3U-EK (connection of PSRAM and LCD on EBI with the DMA).

Regards,

Thanks a lot, great !

That dispels my doubts. Seems I'm on the
right way.

Thanks again

Hi,

I'm new peogramming the SAM3U and I have some problems with the SMC module that manages the PSRAM. I tried to look for the example "connection of PSRAM and LCD on EBI with the DMA" that you posted before, but I had no luck finding it.

My problem is that I don't know how to insert the row and column address for the PSRAM. I tried to manage it like a normal I/O Port, but due to the SMC peripheral controls the pins, I cannot acced to them. Maybe could you tell me, which is the best way to accomplish it?. I would be very thankful if you could help me.

Thanks

>>My problem is that I don't know how to insert the row and column address for the PSRAM.

Not to be stupid, but why would you use a PSRAM part with a multiplexed address bus? Or are you trying to attach an SDRAM? What is the part number of the PSRAM you are using/considering?

The PSRAM I'm planning to use is the AS7C31026B (3.3V 64K x 16 CMOS). I know that the adress as well as the data must be introduced parallel. That's why I use in this case 16 pins for the address and 16 pins for the data. My problem is that these pins are controlled by the SMC modul and I don't find the way to introduce the address and the data using the modul. I could introduce these information configuring the pins as I/O in the SAM3U but then I would lose the characteristics of the SMC module of controlling the times of the other signals (NRD, NWE) between each read and write to the PSRAM. If I'm wrong please tell me, how I should understand it. Thanks

Ok, so why wouldn't that work *exactly* like the part used by the AT91SAM3U-EK, just with slightly fewer higher order address bits?

See schematic/wiring, pg 38
http://www.atmel.com/dyn/resources/prod ... oc6478.pdf

The address bus is linear, and not multiplexed, the row/column is an internal implementation detail of the part, I don't see any consequence of that to the SAM3U.

The PSRAM is mapped directly into the SAM3U's address space, you'd access it just like any other memory attached to the bus. If you configure like the SAM3U-EK it will reside at 0x60000000..0x6001FFFF. Any of this making sense?

A0 of the PSRAM connects to A1 on the SAM3U
A1 of the PSRAM connects to A2 on the SAM3U
..
A15 of the PSRAM connects to A16 on the SAM3U

/// EBI
#define PIN_EBI_DATA_BUS {0xfe01fe00, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}, \
{1 << 6, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}
#define PIN_EBI_NCS0 {1 << 20, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}
#define PIN_EBI_NRD {1 << 19, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}
#define PIN_EBI_NWE {1 << 23, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP}
#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
#define PIN_EBI_PSRAM_NBS {1 << 7, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \
{1 << 15, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}
#define PIN_EBI_A1 {1 << 8, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}

#define BOARD_EBI_PSRAM 0x60000000
#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \
PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1

I didn't take it like an extension of the RAM memory of the SAM and that was my problem. I know I have to include the size of the PSRAM memory for the linker script. Where do I have to set this?. There is in IAR a board.h file where the size is defined as follow:

#define BOARD_PSRAM_SIZE (0x10000) // PSRAM size 64KBytes

but I don't know if that is everything what I have to change, so that the linker uses this information. Thanks for the help

It is a 128 K BYTE part

#define BOARD_PSRAM_SIZE (0x20000) // PSRAM size 128KBytes (64K x16 = 128K x8)

Keil defines the memory map for the linker in it's own configuration tab.

In Keil I know where the configuration tab finds but I have no idea how I could do that with IAR. When I enter to the configuration file in IAR with "configuration/linker", I can adjust the size just of the RAM but it doesn't let me, like Keil, to change the size of an external memory. Do do know maybe how I can do it? Or do I have to change the linker script by hand to accomplish that?

I'd imagine you'd do it with an ICF file, and the ICF editor, but what I've seen of the SAM3U series the memories aren't always contiguous.

You also what you want in internal SRAM, vs external PSRAM, the former is single cycle, and the latter will be slower. You'd want to insure the stack stays on the internal SRAM, or anything that is used frequently.

One for an STM32 would look like this, you'd have to adapt it for the SAM3U

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000200 ;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/


define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];

define symbol __region_PSRAM_start__ = 0x60000000;
define symbol __region_PSRAM_end__ = 0x6001FFFF;

define region PSRAM_region = mem:[from __region_PSRAM_start__ to __region_PSRAM_end__];

define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

initialize by copy { readwrite };
do not initialize { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, block CSTACK };
place in PSRAM_region { readwrite, block HEAP };