Hi all,

I'm using Linux 3.0.3, with my custom board design based on AT91SAM9G45-EK.

I'm getting spi overrun errors when I increase the speed of my SPI communication. My application needs higher speed and I need to fix this problem.

People have talked about this issue in the past but with no conclusive answers and it seems to me that the relevant patches were already applied to the main line kernel long time back.

Any inputs?

-PJ

I'm adding some observations to the above issue (may help someone understanding the problem better):

I also have an LCD.

If I decrease the LCD Clock then I can run the SPI at the the stated max speed that my application requires. But in this case LCD flickers.

If I run the LCD at the req speed (for proper display) then I have to reduce the SPI speed for the SPI to work properly.

There is clearly a peripheral bus contention. But what I fail to understand is, how is there a violation in the bus usage?

-PJ

> People have talked about this issue in the past but with no conclusive answers

That brings back some memories, as I tested some of those patches and even authored another. The gist of the matter is that there is one Atmel SPI peripheral and one Atmel device driver, but some implementations in AVR32 and AT91SAM SoCs seem to have their own quirks. Some devices were plagued by HW errata; I was able to get my board to work acceptably.

> it seems to me that the relevant patches were already applied to the main line kernel long time back.

Yes, the biggie was the DMA chaining patch.

>If I decrease the LCD Clock then I can run the SPI at the the stated max speed that my application requires. But in this case LCD flickers.
> If I run the LCD at the req speed (for proper display) then I have to reduce the SPI speed for the SPI to work properly.

Seems like you've done a good job of investigating this issue. Looks like you've hit an I/O bandwidth ceiling.

> There is clearly a peripheral bus contention.

Yes, that will occur when a lot of I/O is scheduled.
Can you calculate how much I/O bandwidth each device needs?
Can you calculate optimal transfer sizes, and how much latency each device can tolerate?

> But what I fail to understand is, how is there a violation in the bus usage?

There's no indication that there is a "violation". The SPI overrun is a latency issue because the PDC was already in use.

IIRC the PDC can be configured for min and max transfer sizes as well as priority. You should look at what the default configuration is, and perhaps start tweaking the values. Interrupt priorities in the Bus Matrix might also need tweaking.

The SPI overrun is like missing (not servicing) an unlatched interrupt. Essentially you have to evaluate the PDC and DMA transfers just like the CPU and interrupts: you do not want a high-priority event to hog the resource (e.g. CPU or PDC) and starve out low-priority event(s). You have to balance each event's priority, frequency of occurrence and service time so that latencies for all events are minimized to acceptable times.

Regards