Thank you.
When SAM-BA detect and initialized the NAND Flash, Why I need to confirm the content of it?
I haven't any idea for my problem.
Only I know the problem is in the bootstrap.
I don't get my answer, sorry.
Do need any code available in the following lines in the boot strap?
Quote:
/* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC */
No code is available here.
I put the hw_init() function here. Please see and if I change it inform me.
Code:
void hw_init(void)
{
unsigned int cp15;
/* Configure PIOs */
const struct pio_desc hw_pio[] = {
#ifdef CFG_DEBUG
{"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Disable watchdog */
writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
/* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC */
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure CP15 */
cp15 = get_cp15();
cp15 |= I_CACHE;
set_cp15(cp15);
/* Configure the PIO controller */
pio_setup(hw_pio);
/* Configure the EBI Slave Slot Cycle to 64 */
writel( (readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3));
#ifdef CFG_DEBUG
/* Enable Debug messages on the DBGU */
dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
dbg_print("Start AT91Bootstrap...\n\r");
#endif /* CFG_DEBUG */
#ifdef CFG_SDRAM
/* Initialize the matrix */
writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SDRAM Controller */
sdram_init( AT91C_SDRAMC_NC_9 |
AT91C_SDRAMC_NR_13 |
AT91C_SDRAMC_CAS_2 |
AT91C_SDRAMC_NB_4_BANKS |
AT91C_SDRAMC_DBW_32_BITS |
AT91C_SDRAMC_TWR_2 |
AT91C_SDRAMC_TRC_7 |
AT91C_SDRAMC_TRP_2 |
AT91C_SDRAMC_TRCD_2 |
AT91C_SDRAMC_TRAS_5 |
AT91C_SDRAMC_TXSR_8, /* Control Register */
(MASTER_CLOCK * 7)/1000000, /* Refresh Timer Register */
AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
#endif /* CFG_SDRAM */
}
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