Hi All,

I was looking the the doc for the AT91SAM9G20 specifically around the USART clock settings.

In one mode, it allows you to use the MCK divided by a DIV. It says that value is product specific. Does that mean it can only be 8?

Is is their a place you can set it?

Glen

The baud rate divisor handles the bulk of the work. You then have 8 or 16 times oversampling in terms of bit-centering the incoming data.

EDIT: Nevermind, the DIV8 is designed to get the MCK to a lower frequency, figure if the MCK gets to be much faster in newer generations of parts a bigger prescale might be helpful to get to lower baud rates.

Hi!
I guess it is similar to AT91SAM7 and AT91SAM9G45. Check the US_MR register, namely:
- USCLKS - bits 4,5 - MCK or MCK/8
- OVER - bit 19 - you can select 8 or 16 times oversampling

You can also tune up the baud rate with the fractional divider. Check the US_BRGR register; bits: 16, 17, 18.

Is that what are you looking for? I hope it was of some help.

Best regards
Przemyslaw Baranski