Just got a EOL notice from Micron. They die shrunk the 29F2G08 2 Gbit (256 MByte) NAND Flash and now recommend 4 bit ECC per 528 Bytes instead of 1 bit ECC per 528 bytes. As far as I can tell, both HW and SW ECC for the AT91SAM9G20 is 1 bit. I would assume something like this is going to affect Linux code, u-boot code, and SAM-BA, right? I wonder if the Linux, uboot, and other development communities are aware of this change??

Also, it looks like they added an internal 4 bit ECC engine to the new die as well.

I am seeing the same issue on an AT91SAM93X5 based board. The other issue seems to be that the layout of the ECC bytes in the spare area of each page is different on the newer chips. SAM-BA has options to increase the amount of bits of ECC used but it seems to assume that the ECC bytes are all contiguous in the spare area (64B spare area), which it is not anymore. This causes ECC errors when attempting to read data from the flash due to the incompatible ECC schemas. Also, it seems SAM-BA, at91bootstrap, u-boot, linux kernel are not setup to enable the internal ECC controller on the nand die. There are also a lot of limitations on what commands are even covered by the internal ECC controller which would further complicate using it. Is it better to just use software ECC and skip over this issue with PMECC or the internal ECC controller on the nand die?

I'm having the same trouble.
Did anyone successully recompiled samba in order to send to the nand the command to enable the on-die ecc management?
thanks