Hi,

I'm still relatively new to the AT91SAM7X512...

I've developed a simple bootloader that (using SAM-BA) I've loaded into flash. It seems fine. It's using PIT and DBGU interrupts. ...

But once in a while, I'd like to "reset" it so that it boots from the internal ROM, but *WITHOUT* having to assert the ERASE pin (and resetting). It seems (?) to me that what I WANT to do is to clear the GPNVM2 bit in EFC0/MC_FSR. I do this via:

EFC0/MC_FMR <- 00300100 // FMCN = 0x30 (clocks per uS for 48MHz Master Clock), FWS = 1
EFC0/MC_FSR <- 5a00020d // KEY = 0x5a, PAGEN = 2 (for GPNVM2), FCMD = 0xd (CGPB)

THEN IT HANGS! But it seems to have worked. That is, when I cycle power, it comes up in the SAM-BA ROM.

Similarly, when I try to write/program flash, I do..

EFC0/MC_FMR <- 00480100 // FMCN = 0x48 (clocks per 1.5 uS for 48MHz Master Clock), FWS = 1
EFC0/MC_FSR <- 5a008001 // KEY = 5a, PAGEN = 0x80 (for page at 0x00108000), CMD = 1 (WP)

AND IT HANGS TOO. But when I assert RESET, it boots okay and the flash was in fact written.

(I'm executing this code from SRAM.)

Any thoughts? What am I missing?

Thanks and regards,

Tom

Hi!
You can see what is going on:
1) prefetch abort - some part of your code is run from FLASH which is at the moment self-reprogramming. Then you should doublecheck your code. To calculate the address of the instruction that caused the exception: r14 - 4
2) data abort - your program refer to undefined data address. To calculate the address of the instruction that cause the exception: r14 - 8

Hope this helps

Bingo!

Yes.. even though my "applet" was running from SRAM, the PIT interrupt handler was running from flash. I disabled interrupts in the applet and it seems fine now.

Thanks 1e6!

Regards,

Tom