Hi,
iam new to the AT91s. I read the Datasheed of the SAM7S32 and want to make an ADC with using the DMA Controller to sample ~1000 Values at 250Khz with 8Bit Resolution.

It´s not clear to me how the ADC triggers the PDC. The Datasheed says the PDC is triggert when "TXRDY and RXRDY Signals" occour. Does the ADC send out this Singals to the Bus automaticly when it finished a conversation? What are this for Singals?

I read,the ADC can be triggert by one of the Countersoutputs Rising Edge.But my device (CCD-CIS Sensor) has only stable data at the falling edge of its clock. It is possible to configure one Timer with a Phasedifferent of Pi? So one Timer will clock the external Device and the other will clock the ADC.

Thank you for ur help und sorry for my poor English.

I found that it is best to search for "PDC" in the ADC section of the specification to find all references to PDC related info.

The answer is that the DRDY signal initiates the DMA xfer.

Theodor, read the PDC section of the datasheet to understand how DMA works. The signals you are referring to would probably be flags in the ADC's status register. You can program an interrupt to call your function when the flag is set.

Hi

The DMA operation of the ADC is quite easy to use.
The following code is about all that is needed to configure it:

ADC_RPR = (unsigned long)adc_setup->int_adc_result; // transfer start location
ADC_RCR = adc_setup->int_samples; // transfer count
ADC_PTCR = PDC_RXTEN; // enable transfer
ADC_IER = ADC_ENDRX; // enable interrupt on transfer complete

This causes the PDC to store adc_setup->int_samples samples in the buffer adc_setup->int_adc_result.
When all samples have completed, an end of transfer interrupt is generated.

The sample triggering can be controlled by rising edges on ADTRG. If you would prefer falling edges it may be easiest to insert an inverter in the path.

Regards

Mark

http://www.uTasker.com

Hi Mark,

If the PDC "Receiver Counter" reaches zero, the next PDC received data will automaticcally write to the location which "Receiver Next Pointer" point to ?

I can't find how the "Receiver Next pointer" works in the manual.

Regards

Samuel

Samuel

When the counter reaches 0 the DMA operation will terminate so no more copies take place. There is an interrupt generated when this happens so that following operation can be started if desired.

Regards

Mark

www.uTasker.com

Hi Mark,

I find this from the manual (Page of 141 at DOC6120.pdf)
"The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to
re-enable the triggers."

Everything works, my AD rate can reach 500K! It is very quick!
It can reach only 100K if use TIOA pulse and interrupt.

Regards
Samuel

Hi Samuel

This is the ping-pong buffer operation that the DMA supports. It doesn't have to be used though but enables high throughput by allowing the interrupt from the end of the first block to prepare the 'over-next' buffer while the next buffer is immediately used by the DMA.

The USB controller uses the same method so that it can achieve isochronous rates - using a single buffer would mean that the process is highly dependent on the reaction time of the interrupt of a single buffer and so there would be 'dead-periods'. Also the SSC can use the same technique to maintain high throughput rates without losing synchronisation. http://www.utasker.com/docs/uTasker/uTaskerSSC.PDF

Regards

Mark

www.uTasker.com