Kernel panic in transfer load if booted from dataflash

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gerator
Posts: 6
Joined: Tue May 23, 2006 3:21 pm

Kernel panic in transfer load if booted from dataflash

Wed Jul 19, 2006 2:32 pm

Hi.

I'm working on Portux920T board, a board partially based on atmel's
evaluation board. It has been modified to add a dataflash memory.
I want to try the possibilities and then do my own desing. That's why I
want to boot from a tiny dataflash.

I have compiled a 2.6.17 kernel with the maxim patch, and created a
rootfs as initrd. If I boot from parallel flash all seems to go right.
U-boot (1.1.2) gets started, then I (manually) load kernel and initrd in
SDRAM, and finally the system goes up smoothly.

The problem comes when I want to boot from dataflash. I start the first
stage loader (the atmel one or a custom one), then U-boot (1.1.4) gets
started, and finally I do the same as in the other mothod and the system
boots. At first, all seems to be working, in fact, I can work in the
system. But if I do some heavy transfer, for example:

dd if=/dev/zero of=/root/delete bs=1k count=3k (count=2k works!!! :()

Then I get the panic at the end of the post.

I thought it could be a problem in SDRAM initialization or bus width
selection, but both seems to be OK. So could it be a kernel problem?

Any help is welcomed.

Thanks.

Code: Select all


Unable to handle kernel NULL pointer dereference at virtual address
00000000
pgd = c3278000
[00000000] *pgd=23d86031, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#1]
Modules linked in:
CPU: 0
PC is at __wake_up_common+0x28/0x7c
LR is at __init_begin+0x3fff8000/0x30
pc : [<c0030ab8>]    lr : [<00000000>]    Not tainted
sp : c038dcdc  ip : c038dd08  fp : c038dd04
r10: 00000003  r9 : c038dd20  r8 : 00000000
r7 : c02ac000  r6 : c0000000  r5 : c02ac000  r4 : 00000001
r3 : 00000000  r2 : 00000001  r1 : 00000003  r0 : c0000000
Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  Segment user
Control: C000717F  Table: 23278000  DAC: 00000015
Process dd (pid: 699, stack limit = 0xc038c198)
Stack: (0xc038dcdc to 0xc038e000)
dcc0:
00000013
dce0: c02ac000 00000400 c02ac000 00000000 01690400 00000000 c038dd1c
c038dd08
dd00: c0030b38 c0030aa0 c038dd20 c02ac000 c038dd34 c038dd20 c0047db8
c0030b1c
dd20: c02ac000 00000000 c038dd48 c038dd38 c0050218 c0047d98 00000400
c038dde8
dd40: c038dd4c c0052140 c00501dc 00000400 000aa450 00000400 c3f533c8
c0210b84
dd60: c3f53464 c3f562a0 00000001 c038de78 00000000 00000400 c038df20
0003007c
dd80: 00000001 00000000 c02ac000 00000000 01610400 0000009a 1914e1cd
c038ddcc
dda0: c038ddc8 c038ddb0 c0038f4c c0038eb4 c3f533c8 00000000 c038ddcc
c038ddec
ddc0: 01690000 00000000 c038de1c 00000000 01690000 00000000 c3f562a0
c038de74
dde0: c038ddf0 c0052988 c0051c88 01690000 00000000 c038df78 00000000
00000400
de00: 00000000 00000400 c038df78 c038df20 c038de78 00000001 00000400
01690000
de20: 00000000 00000000 c038df0c 00000001 c038df0c c038c000 c024fd40
c038de60
de40: c038de4c c003d350 c004962c c038deb8 c3c007c0 c038de78 00000000
00000000
de60: c038c000 00000000 c038df10 c038de78 c0052a38 c00524e8 c3c91d00
00000001
de80: 00000000 00000001 ffffffff c3f562a0 00000000 00000000 00000000
00000000
dea0: c3c007c0 00000000 00000000 c038c000 c3c007c0 c0047c74 c038deb8
c038deb8
dec0: c003cfd4 c003ce90 c038df00 c038ded8 c014a5c8 c003cf9c c038c000
c038c000
dee0: c0257db4 00000100 c014a5d0 c038df14 c3f53438 c3f53464 000aa050
c3f533c8
df00: c3f562a0 c038df50 c038df14 c0052b80 c00529c8 c0119140 c038df14
c038df78
df20: 000aa050 00000400 c3f562a0 00000400 000aa050 c038c000 c038df78
c038c000
df40: 00000000 c038df74 c038df54 c006af2c c0052b48 c3f562c0 c3f562a0
c038df78
df60: 01690000 00000000 c038dfa4 c038df78 c006b064 c006ae7c 01690000
00000000
df80: 00000000 00000400 00000400 000aa050 00000004 c001fea4 00000000
c038dfa8
dfa0: c001fd00 c006b028 00000400 00000400 00000004 000aa050 00000400
00000000
dfc0: 00000400 00000400 000aa050 00000004 00000400 beb69f31 00000000
beb69f3e
dfe0: 00000000 beb69d44 00003750 4010fc90 60000010 00000004 cc37c431
dc31cc33
Backtrace:
[<c0030a90>] (__wake_up_common+0x0/0x7c) from [<c0030b38>] (__wake_up
+0x2c/0x34)
[<c0030b0c>] (__wake_up+0x0/0x34) from [<c0047db8>] (__wake_up_bit
+0x30/0x38)
 r4 = C02AC000
[<c0047d88>] (__wake_up_bit+0x0/0x38) from [<c0050218>] (unlock_page
+0x4c/0x58)
[<c00501cc>] (unlock_page+0x0/0x58) from [<c0052140>]
(generic_file_buffered_write+0x4cc/0x5dc)
 r4 = 00000400
[<c0051c78>] (generic_file_buffered_write+0x4/0x5dc) from [<c0052988>]
(__generic_file_aio_write_nolock+0x4b0/0x4e0)
[<c00524d8>] (__generic_file_aio_write_nolock+0x0/0x4e0) from
[<c0052a38>] (__generic_file_write_nolock+0x80/0xac)
[<c00529b8>] (__generic_file_write_nolock+0x0/0xac) from [<c0052b80>]
(generic_file_write+0x48/0xc8)
 r8 = C3F562A0  r7 = C3F533C8  r6 = 000AA050  r5 = C3F53464
 r4 = C3F53438
[<c0052b38>] (generic_file_write+0x0/0xc8) from [<c006af2c>] (vfs_write
+0xc0/0x138)
[<c006ae6c>] (vfs_write+0x0/0x138) from [<c006b064>] (sys_write
+0x4c/0x74)
 r8 = 00000000  r7 = 01690000  r6 = C038DF78  r5 = C3F562A0
 r4 = C3F562C0
[<c006b018>] (sys_write+0x0/0x74) from [<c001fd00>] (ret_fast_syscall
+0x0/0x2c)
 r8 = C001FEA4  r7 = 00000004  r6 = 000AA050  r5 = 00000400
 r4 = 00000400
Code: e1a0a001 e1a04002 e1a08003 e59b9004 (e59e7000)
 <1>Unable to handle kernel NULL pointer dereference at virtual address
00000000
pgd = c3f5c000
[00000000] *pgd=23e32031, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#2]
Modules linked in:
CPU: 0
PC is at __wake_up_common+0x28/0x7c
LR is at __init_begin+0x3fff8000/0x30
pc : [<c0030ab8>]    lr : [<00000000>]    Not tainted
sp : c3e5dde0  ip : c3e5de0c  fp : c3e5de08
r10: 00000003  r9 : c3e5de24  r8 : 00000000
r7 : c001285c  r6 : c00001f0  r5 : c02e8800  r4 : 00000001
r3 : 00000000  r2 : 00000001  r1 : 00000003  r0 : c00001f0
Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  Segment user
Control: C000717F  Table: 23F5C000  DAC: 00000015
Process sh (pid: 681, stack limit = 0xc3e5c198)
Stack: (0xc3e5dde0 to 0xc3e5e000)
dde0: 00000013 c02e8800 00000000 c001285c 4001e000 c3f0c878 c0017960
c3e5de20
de00: c3e5de0c c0030b38 c0030aa0 c3e5de24 c02e8800 c3e5de38 c3e5de24
c0047db8
de20: c0030b1c c02e8800 00000000 c3e5de4c c3e5de3c c0050218 c0047d98
00000000
de40: c3e5de7c c3e5de50 c005ce40 c00501dc 00000002 23e400df 00000001
c001285c
de60: 00000078 4001e000 00000800 c0017960 c3e5dec8 c3e5de80 c005dc6c
c005cdd8
de80: c3f5d000 c00179a0 23e400df c00545f8 c00541d8 c3e5deb0 c3f5d000
c0054f7c
dea0: ffffffeb c03f4860 c001285c c0017960 c0017994 c3e5dfb0 4001e40c
c3e5df04
dec0: c3e5decc c0026394 c005d724 c3c007c0 c0315320 00000800 0000081f
ffffffff
dee0: c020c06c 0000081f c3e5dfb0 4001e40c 00000005 4001e000 c3e5dfac
c3e5df08
df00: c0026608 c00262c4 c3e5df8c c3e5df18 c0037aa0 c0047af4 c3e5df24
c016bacc
df20: c016b8c0 c03f4910 c3e5c000 00000000 c03f4860 be881bc4 ffffffff
00000000
df40: c03f4860 c0030a78 00000000 00000000 00000000 c03f4860 c0030a78
00100100
df60: 00200200 ffffffea 00000000 000ac1a5 00000072 c001fea4 c3e5c000
00000000
df80: c3e5dfa4 c3e5df90 c0037c24 ffffffff 4001e720 00009fa0 00000000
be881b84
dfa0: 00000000 c3e5dfb0 c001fcc8 c00265dc 099fbecc 4001e264 000000fc
0000010b
dfc0: 0000020c 4001e720 00009fa0 00000000 be881b84 00000005 4001e000
be881b70
dfe0: 0000a74c be881ad0 40007af4 40007b04 60000010 ffffffff 00000000
00000000
Backtrace:
[<c0030a90>] (__wake_up_common+0x0/0x7c) from [<c0030b38>] (__wake_up
+0x2c/0x34)
[<c0030b0c>] (__wake_up+0x0/0x34) from [<c0047db8>] (__wake_up_bit
+0x30/0x38)
 r4 = C02E8800
[<c0047d88>] (__wake_up_bit+0x0/0x38) from [<c0050218>] (unlock_page
+0x4c/0x58)
[<c00501cc>] (unlock_page+0x0/0x58) from [<c005ce40>] (do_wp_page
+0x78/0x3bc)
 r4 = 00000000
[<c005cdc8>] (do_wp_page+0x0/0x3bc) from [<c005dc6c>] (__handle_mm_fault
+0x558/0x608)
[<c005d714>] (__handle_mm_fault+0x0/0x608) from [<c0026394>]
(do_page_fault+0xe0/0x214)
[<c00262b4>] (do_page_fault+0x0/0x214) from [<c0026608>] (do_DataAbort
+0x3c/0xa0)
[<c00265cc>] (do_DataAbort+0x0/0xa0) from [<c001fcc8>]
(ret_from_exception+0x0/0x10)
 r8 = BE881B84  r7 = 00000000  r6 = 00009FA0  r5 = 4001E720
 r4 = FFFFFFFF
Code: e1a0a001 e1a04002 e1a08003 e59b9004 (e59e7000)
 <1>Unable to handle kernel NULL pointer dereference at virtual address
00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 17 [#3]
Modules linked in:
CPU: 0
PC is at __wake_up_common+0x28/0x7c
LR is at __init_begin+0x3fff8000/0x30
pc : [<c0030ab8>]    lr : [<00000000>]    Not tainted
sp : c0349d70  ip : c0349d9c  fp : c0349d98
r10: 00000003  r9 : c0349db4  r8 : 00000000
r7 : 00000200  r6 : c0000060  r5 : 00000002  r4 : 00000001
r3 : 00000000  r2 : 00000001  r1 : 00000003  r0 : c0000060
Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  Segment kernel
Control: C000717F  Table: 23F5C000  DAC: 00000017
Process mmcqd (pid: 664, stack limit = 0xc0348198)
Stack: (0xc0349d70 to 0xc034a000)
9d60:                                     00000093 00000002 c02d48a0
00000200
9d80: c3f7ddd8 00000000 00000200 c0349db0 c0349d9c c0030b38 c0030aa0
c0349db4
9da0: c3bfd574 c0349dc8 c0349db4 c0047db8 c0030b1c c3bfd574 00000002
c0349de0
9dc0: c0349dcc c0047de4 c0047d98 c3bfd574 20000093 c0349df0 c0349de4
c006c240
9de0: c0047dd0 c0349e2c c0349df4 c006cca8 c006c220 c0348000 c0349e60
c0349e84
9e00: c3c21544 c3c787dc c3c21548 c0349e5c c0349e1c c03512a0 00000000
c03512a0
9e20: c0349e44 c0349e30 c006d9cc c006cb98 c03512a0 c006d954 c0349e5c
c0349e48
9e40: c0070de8 c006d964 00000000 c0349ee4 c0349ea4 c0349e60 c010326c
c0070d68
9e60: 00000000 c0349e64 c0349e64 c0349eb8 00000005 00000000 00000000
c3f7ddd8
9e80: c0349ee4 c3c61000 c3c21540 c3c21544 c3c787dc c3c21548 c0349eb4
c0349ea8
9ea0: c0103620 c0103108 c0349fa0 c0349eb8 c015f2bc c0103620 0000000d
a95c0000
9ec0: 00000900 0003a6e4 0003a6e5 0003a6e3 00000015 00000005 00000000
00000000
9ee0: c0349e84 c0349ef8 c0349f50 00000000 c0349e94 c015cea0 00000018
0e97b600
9f00: 00000900 0003a6e4 0003a6e5 0003a6e3 00000035 00000000 00000000
c0349f50
9f20: c0349ee4 0000000c 00000000 00000000 00000000 00000000 00000000
0000001d
9f40: 00000000 00000000 00000000 00000000 0e4e1c00 00000000 00000009
00000200
9f60: 00000001 00000000 00000100 00000200 00000000 c0349ee4 00000001
c3c91f20
9f80: c3c2155c c3c21544 c0348000 00000000 c3c21554 c0349ff4 c0349fa4
c015e570
9fa0: c015f0d8 00000000 c036c5a0 c0030a78 00000000 00000000 00000000
c036c5a0
9fc0: c0030a78 c3c21554 c3c21554 00000000 00000000 00000000 00000000
00000000
9fe0: 00000000 00000000 00000000 c0349ff8 c003654c c015e410 dc33cc33
cc33cc31
Backtrace:
[<c0030a90>] (__wake_up_common+0x0/0x7c) from [<c0030b38>] (__wake_up
+0x2c/0x34)
[<c0030b0c>] (__wake_up+0x0/0x34) from [<c0047db8>] (__wake_up_bit
+0x30/0x38)
 r4 = C3BFD574
[<c0047d88>] (__wake_up_bit+0x0/0x38) from [<c0047de4>] (wake_up_bit
+0x24/0x28)
[<c0047dc0>] (wake_up_bit+0x0/0x28) from [<c006c240>] (unlock_buffer
+0x30/0x34)
 r5 = 20000093  r4 = C3BFD574
[<c006c210>] (unlock_buffer+0x0/0x34) from [<c006cca8>]
(end_buffer_async_write+0x120/0x18c)
[<c006cb88>] (end_buffer_async_write+0x0/0x18c) from [<c006d9cc>]
(end_bio_bh_io_sync+0x78/0x88)
 r6 = C03512A0  r5 = 00000000  r4 = C03512A0
[<c006d954>] (end_bio_bh_io_sync+0x0/0x88) from [<c0070de8>] (bio_endio
+0x90/0x9c)
 r5 = C006D954  r4 = C03512A0
[<c0070d58>] (bio_endio+0x0/0x9c) from [<c010326c>]
(__end_that_request_first+0x174/0x500)
 r5 = C0349EE4  r4 = 00000000
[<c01030f8>] (__end_that_request_first+0x0/0x500) from [<c0103620>]
(end_that_request_chunk+0x10/0x14)
[<c0103610>] (end_that_request_chunk+0x0/0x14) from [<c015f2bc>]
(mmc_blk_issue_rq+0x1f4/0x2fc)
[<c015f0c8>] (mmc_blk_issue_rq+0x0/0x2fc) from [<c015e570>]
(mmc_censored_thread+0x170/0x1bc)
 r8 = C3C21554  r7 = 00000000  r6 = C0348000  r5 = C3C21544
 r4 = C3C2155C
[<c015e400>] (mmc_censored_thread+0x0/0x1bc) from [<c003654c>] (do_exit
+0x0/0x7c8)
Code: e1a0a001 e1a04002 e1a08003 e59b9004 (e59e7000)
 <1>Unable to handle kernel NULL pointer dereference at virtual address
00000000
pgd = c0008000
[00000000] *pgd=2000f031, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#4]
Modules linked in:
CPU: 0
PC is at __wake_up_common+0x28/0x7c
LR is at __init_begin+0x3fff8000/0x30
pc : [<c0030ab8>]    lr : [<00000000>]    Not tainted
sp : c0317ddc  ip : c0317e08  fp : c0317e04
r10: 00000003  r9 : c0317e20  r8 : 00000000
r7 : c3e34568  r6 : c0000160  r5 : 00000003  r4 : 00000001
r3 : 00000000  r2 : 00000001  r1 : 00000003  r0 : c0000160
Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  Segment user
Control: C000717F  Table: 20008000  DAC: 00000015
Process init (pid: 1, stack limit = 0xc0316198)
Stack: (0xc0317ddc to 0xc0318000)
7dc0:
00000013
7de0: 00000003 00000001 c3e34568 c3e3443c 00000000 c020f004 c0317e1c
c0317e08
7e00: c0030b38 c0030aa0 c0317e20 c030e9b8 c0317e34 c0317e20 c0047db8
c0030b1c
7e20: c030e9b8 00000003 c0317e4c c0317e38 c0047de4 c0047d98 c030e8b0
c0097b54
7e40: c0317e5c c0317e50 c0084c38 c0047dd0 c0317e74 c0317e60 c0085120
c0084c30
7e60: c030e8b0 00000001 c0317e88 c0317e78 c00842dc c0085058 c3e34534
c0317e98
7e80: c0317e8c c008226c c0084260 c0317eb4 c0317e9c c00828cc c0082210
c0316000
7ea0: 00000001 c3e34470 c0317edc c0317eb8 c0082bfc c00827d8 c3e3443c
c03f4860
7ec0: c03f4860 c03ef560 c3e3443c 00000005 c0317ef0 c0317ee0 c0099eb0
c0082b0c
7ee0: 00000000 c0317f14 c0317ef4 c0035a68 c0099ea8 000002a9 c03f4860
c03f4860
7f00: 00000000 c03f4918 c0317f8c c0317f18 c0037818 c003575c c0317f80
c0317f28
7f20: c004ab3c c0313d70 c0316000 00000001 c0313cc0 bee9ce48 ffffffff
00000000
7f40: c0313cc0 c0030a78 00000000 00000000 00000000 c0313cc0 c0030a78
c0315e28
7f60: c0315e28 ffffffea bee9ce48 ffffffff 00000072 c001fea4 c0316000
40178000
7f80: c0317fa4 c0317f90 c0037c24 c0036ff4 00000000 00000001 00000000
c0317fa8
7fa0: c001fd00 c0037bfc 00000001 bee9ce48 ffffffff bee9ce48 00000001
00000000
7fc0: 00000001 bee9ce48 ffffffff bee9cf34 00000001 0000cb04 40178000
00000000
7fe0: 4017b750 bee9ce30 00000000 400ed588 60000010 ffffffff dc33cc33
cc33cc31
Backtrace:
[<c0030a90>] (__wake_up_common+0x0/0x7c) from [<c0030b38>] (__wake_up
+0x2c/0x34)
[<c0030b0c>] (__wake_up+0x0/0x34) from [<c0047db8>] (__wake_up_bit
+0x30/0x38)
 r4 = C030E9B8
[<c0047d88>] (__wake_up_bit+0x0/0x38) from [<c0047de4>] (wake_up_bit
+0x24/0x28)
[<c0047dc0>] (wake_up_bit+0x0/0x28) from [<c0084c38>] (wake_up_inode
+0x18/0x1c)
 r5 = C0097B54  r4 = C030E8B0
[<c0084c20>] (wake_up_inode+0x0/0x1c) from [<c0085120>]
(generic_delete_inode+0xd8/0x108)
[<c0085048>] (generic_delete_inode+0x0/0x108) from [<c00842dc>] (iput
+0x8c/0xa0)
 r5 = 00000001  r4 = C030E8B0
[<c0084250>] (iput+0x0/0xa0) from [<c008226c>] (dentry_iput+0x6c/0x70)
 r4 = C3E34534
[<c0082200>] (dentry_iput+0x0/0x70) from [<c00828cc>] (prune_dcache
+0x104/0x13c)
[<c00827c8>] (prune_dcache+0x0/0x13c) from [<c0082bfc>]
(shrink_dcache_parent+0x100/0x10c)
 r6 = C3E34470  r5 = 00000001  r4 = C0316000
[<c0082afc>] (shrink_dcache_parent+0x0/0x10c) from [<c0099eb0>]
(proc_pid_flush+0x18/0x24)
[<c0099e98>] (proc_pid_flush+0x0/0x24) from [<c0035a68>] (release_task
+0x31c/0x354)
 r4 = 00000000
[<c003574c>] (release_task+0x0/0x354) from [<c0037818>] (do_wait
+0x834/0xb78)
 r8 = C03F4918  r7 = 00000000  r6 = C03F4860  r5 = C03F4860
 r4 = 000002A9
[<c0036fe4>] (do_wait+0x0/0xb78) from [<c0037c24>] (sys_wait4+0x38/0x44)
[<c0037bec>] (sys_wait4+0x0/0x44) from [<c001fd00>] (ret_fast_syscall
+0x0/0x2c)
 r4 = 00000001
Code: e1a0a001 e1a04002 e1a08003 e59b9004 (e59e7000)
 <0>Kernel panic - not syncing: Attempted to kill init!
User avatar
koan
Contact:
Location: Bergamo, Italia
Posts: 212
Joined: Wed May 12, 2004 6:59 pm

Mon Jul 24, 2006 7:27 pm

Solution could be not as easy as it appears,
details about your hw system would help
Which Dataflash are you using ?

BTW consider upgrade to u-boot-1.1.4

--
Marco Cavallini
Koan s.a.s. - Software Engineering
Linux and WinCE solutions for Embedded and Real-Time Software
- Atmel AT91 ARM Third Party Consultant
Via Pascoli, 3 - 24121 Bergamo - ITALIA
Tel. +39-(0)35-255.235 - Fax +39-178-223.9748
http://www.KoanSoftware.com - http://www.KaeilOS.com
gerator
Posts: 6
Joined: Tue May 23, 2006 3:21 pm

Tue Jul 25, 2006 9:57 am

I'm currently using uboot 1.1.4.

I'm using a board based on an at91rm9200 (PQFP package), Two memory chips from Micron 48LC16M16 with a 32-bit bus width setup. The dataflash part is AT45DB321B (32Mbit). And the parallel flash part is AM29LV641. As far as I have analized the board, it's based on Atmel's eval board design.

As the problem only reproduces when booting from dataflash (same boot process as parallel flash except from uboot load) I think it could be some initialization problem but both memory and clock seems to be properly configured.

Bye.
User avatar
koan
Contact:
Location: Bergamo, Italia
Posts: 212
Joined: Wed May 12, 2004 6:59 pm

Re: Kernel panic in transfer load if booted from dataflash

Wed Jul 26, 2006 10:52 am

gerator wrote: I'm working on Portux920T board, a board partially based on atmel's
evaluation board. It has been modified to add a dataflash memory.
I want to try the possibilities and then do my own desing. That's why I
want to boot from a tiny dataflash.

The problem comes when I want to boot from dataflash. I start the first
stage loader (the atmel one or a custom one), then U-boot (1.1.4) gets
started, and finally I do the same as in the other mothod and the system
boots.
As you can see in our website, of course we know Portux very well
You have to customize u-boot in order to support your hw changes, like dataflash, not included in standard Portux.

--
Marco Cavallini
Koan s.a.s. - Software Engineering
Linux and WinCE solutions for Embedded and Real-Time Software
- Atmel AT91 ARM Third Party Consultant
Via Pascoli, 3 - 24121 Bergamo - ITALIA
Tel. +39-(0)35-255.235 - Fax +39-178-223.9748
http://www.KoanSoftware.com - http://www.KaeilOS.com
gerator
Posts: 6
Joined: Tue May 23, 2006 3:21 pm

Thu Jul 27, 2006 11:45 am

Hi.

Portux's uboot config is clearly based on at91rm9200dk and, although it does't feature dataflash, includes dataflash support. The dataflash seems to be optional as the dataflash footprint is on the bottom of the board.

Anyway, I have tried to modify the config for dataflashboot with both 1.1.2 (stock portux uboot) and 1.1.4. I have tried to adapt config for 1.1.4 and defined CFG_ENV_IS_IN_DATAFLASH. Also I make sure SKIP_LOW_LEVEL_INIT is defined, as this is done in the first stage bootloader. This ends with the same result, linux boots ok but it ends giving that kernel panic.

I have tried (again with both versions of uboot) to start from at91rm9200dk config, but it doesn't make any difference.

I post my config:

Code: Select all

/*
 * Rick Bronson <rick@efn.org>
 *
 * Configuation settings for the AT91RM9200DK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK		179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK		59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
/* #define AT91C_MASTER_CLOCK		44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */

#define AT91_SLOW_CLOCK			32768	/* slow clock */

#define CONFIG_ARM920T			1	/* This is an ARM920T Core	*/
#define CONFIG_AT91RM9200		1	/* It's an Atmel AT91RM9200 SoC	*/
#define CONFIG_PORTUX920T		1	/* on a Portux920T Board	*/
#define CONFIG_AT91RM9200DK		1
#undef  CONFIG_USE_IRQ				/* we don't need IRQ/FIQ stuff	*/
#define USE_920T_MMU			1

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_BOOTBINFUNC
#define CONFIG_SKIP_LOWLEVEL_INIT

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CFG_USE_MAIN_OSCILLATOR		1
/* flash */
#define MC_PUIA_VAL	0x00000000
#define MC_PUP_VAL	0x00000000
#define MC_PUER_VAL	0x00000000
#define MC_ASR_VAL	0x00000000
#define MC_AASR_VAL	0x00000000
#define EBI_CFGR_VAL	0x00000000
#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */

/* sdram */
#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define PIOC_BSR_VAL	0x00000000
#define PIOC_PDR_VAL	0xFFFF0000
#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
#define SDRAM		0x20000000 /* address of the SDRAM */
#define SDRAM1		0x20000080 /* address of the SDRAM */
#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL	0x00000002 /* Precharge All */
#define SDRC_MR_VAL1	0x00000004 /* refresh */
#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

#define CONFIG_BAUDRATE 115200
#define CFG_AT91C_BRGR_DIVISOR	33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */

/*
 * Hardware drivers
 */

/* define one of these to choose the DBGU, USART0  or USART1 as console */
#define CONFIG_DBGU
#undef CONFIG_USART0
#undef CONFIG_USART1

#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/

#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */

#define CONFIG_BOOTDELAY      3
 #define CONFIG_ENV_OVERWRITE	1 

#define CONFIG_COMMANDS		\
		       ((CONFIG_CMD_DFL | CFG_CMD_MII |\
			CFG_CMD_DHCP ) & \
		      ~(CFG_CMD_BDI | \
			CFG_CMD_IMI | \
			CFG_CMD_AUTOSCRIPT | \
			CFG_CMD_FPGA | \
			CFG_CMD_MISC | \
			CFG_CMD_LOADS ))

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
#define SECTORSIZE 512

#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1

#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */

#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)

#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/* the following are NOP's in our implementation */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)

#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x2000000  /* 64 megs */

#define CFG_MEMTEST_START		PHYS_SDRAM
#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144

#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_AT91C_USE_RMII

#define CONFIG_HAS_DATAFLASH		1
#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 	2
#define CFG_MAX_DATAFLASH_PAGES 	8192
#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */

#define PHYS_FLASH_1			0x10000000
#define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
#define CFG_FLASH_BASE			PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS		1
#define CFG_MAX_FLASH_SECT		256
#define CFG_FLASH_ERASE_TOUT		(6*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT		(4*CFG_HZ) /* Timeout for Flash Write */

#define CFG_ENV_IS_IN_DATAFLASH		1
#define CFG_ENV_OFFSET			0x30000
#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE			0x10000

#define CFG_LOAD_ADDR		0x21000000  /* default load address */


#define CFG_BOOT_SIZE		0x00 /* 0 KBytes */
#define CFG_U_BOOT_BASE		PHYS_FLASH_1
#define CFG_U_BOOT_SIZE		0x20000 /* 128 KBytes */

#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

#ifndef __ASSEMBLY__
/*-----------------------------------------------------------------------
 * Board specific extension for bd_info
 *
 * This structure is embedded in the global bd_info (bd_t) structure
 * and can be used by the board specific code (eg board/...)
 */

struct bd_info_ext {
	/* helper variable for board environment handling
	 *
	 * env_crc_valid == 0    =>   uninitialised
	 * env_crc_valid  > 0    =>   environment crc in flash is valid
	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
	 */
	int env_crc_valid;
};
#endif

#define CFG_HZ 1000
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
					/* AT91C_TC_TIMER_DIV1_CLOCK */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Thx, bye.

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