Lousy performance on driving a pin.

Discussion around products based on ARM Cortex-A5 core.

Moderator: nferre

Boo
Posts: 1
Joined: Sat Dec 06, 2014 11:50 pm

Lousy performance on driving a pin.

Sun Dec 07, 2014 1:03 am

Hello,
I’m new to Atmel ARM, but quite good with some other architectures.
I’m running SAMA5D36, PCK at 498MHz and MCK at 166MHz (checked).
I configured a pin as output and trying to toggle it as fast as possible, getting very disappointing result with 12MHz max at the pin.
The code is as simple as possible:
extern int main( void )
{
WDT_Disable( WDT ) ;

PIOC->PIO_OER=0x20000000; //output enable
PIOC->PIO_PER=0x20000000; //peripheral enable - set to be driven by PIO
PIOC->PIO_MDDR=0x20000000; //multi-drive disable

while(1)
{
PIOC->PIO_CODR = 0x20000000; // Clear Output Data register
PIOC->PIO_SODR = 0x20000000; // Set Output Data register
}
return 0 ;
}

Compiler generated assembler code was not very clean, I made it strait:

extern int main( void )
{
WDT_Disable( WDT ) ;

PIOC->PIO_OER=0x20000000; //output enable
PIOC->PIO_PER=0x20000000; //peripherial enable - set to be driven by PIO
PIOC->PIO_MDDR=0x20000000; //multi-drive disable

asm volatile (
"mov r1,#-208\n"
"bic r1,r1,#2304\n" //r1 = 0xffffff630 PIO_SODR
"mov r2, r1\n"
"add r2, r2,#4\n" //r2 = 0xffffff634 PIO_CODR

"mov r7,#0x20000000\n"

"l1: str r7,[r1]\n" //shortest code possible
"str r7,[r2]\n"
"b l1");
}
Same 12MHz at the pin.

I tried to make it asymmetric and added empty loop in one part.
asm volatile (
"mov r1,#-208\n"
"bic r1,r1,#2304\n" //r1 = 0xffffff630 PIO_SODR
"mov r2, r1\n"
"add r2, r2,#4\n" //r2 = 0xffffff634 PIO_CODR

"mov r7,#0x20000000\n"
"mov r8,#0x07\n" //delay value


"l1: str r7,[r1]\n" // PIO_SODR
"str r7,[r2]\n" // PIO_CODR

"mov r9,r8\n"
"l2: subs r9,r9,#1\n"
"bne l2\n"

"b l1");

If the delay value is less than 4 - no delay is visible by oscilloscope – core could do some other job while data is travelling to the pin; over 4 it adds 18ns for every empty cycle, giving 9ns per instruction, which gives approx. 111 million instructions per second. That small value I also can’t explain.
It definitely linearly depends on MCK frequency, being free from dependence on PCK (checked some values).From measurements it seems that 7 MCK cycles is needed for internal register to be written.
It is not clear for me at all how “extra” requests are dropped (as far as core can generate much more of them, then performed). It looks like perfect meander at pin with no visible damage or noise.

It is obvious that I do not understand how the whole system is working. I appreciate any comments or suggestions how to make it faster :)).
Best regards, Boo.

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